1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/dmi.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/platform_data/x86/clk-lpss.h> 20 #include <linux/platform_data/x86/pmc_atom.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pwm.h> 24 #include <linux/suspend.h> 25 #include <linux/delay.h> 26 27 #include "internal.h" 28 29 ACPI_MODULE_NAME("acpi_lpss"); 30 31 #ifdef CONFIG_X86_INTEL_LPSS 32 33 #include <asm/cpu_device_id.h> 34 #include <asm/intel-family.h> 35 #include <asm/iosf_mbi.h> 36 37 #define LPSS_ADDR(desc) ((unsigned long)&desc) 38 39 #define LPSS_CLK_SIZE 0x04 40 #define LPSS_LTR_SIZE 0x18 41 42 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 43 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 44 #define LPSS_RESETS 0x04 45 #define LPSS_RESETS_RESET_FUNC BIT(0) 46 #define LPSS_RESETS_RESET_APB BIT(1) 47 #define LPSS_GENERAL 0x08 48 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 49 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 50 #define LPSS_SW_LTR 0x10 51 #define LPSS_AUTO_LTR 0x14 52 #define LPSS_LTR_SNOOP_REQ BIT(15) 53 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 54 #define LPSS_LTR_SNOOP_LAT_1US 0x800 55 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 56 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 57 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 58 #define LPSS_LTR_MAX_VAL 0x3FF 59 #define LPSS_TX_INT 0x20 60 #define LPSS_TX_INT_MASK BIT(1) 61 62 #define LPSS_PRV_REG_COUNT 9 63 64 /* LPSS Flags */ 65 #define LPSS_CLK BIT(0) 66 #define LPSS_CLK_GATE BIT(1) 67 #define LPSS_CLK_DIVIDER BIT(2) 68 #define LPSS_LTR BIT(3) 69 #define LPSS_SAVE_CTX BIT(4) 70 #define LPSS_NO_D3_DELAY BIT(5) 71 72 /* Crystal Cove PMIC shares same ACPI ID between different platforms */ 73 #define BYT_CRC_HRV 2 74 #define CHT_CRC_HRV 3 75 76 struct lpss_private_data; 77 78 struct lpss_device_desc { 79 unsigned int flags; 80 const char *clk_con_id; 81 unsigned int prv_offset; 82 size_t prv_size_override; 83 struct property_entry *properties; 84 void (*setup)(struct lpss_private_data *pdata); 85 bool resume_from_noirq; 86 }; 87 88 static const struct lpss_device_desc lpss_dma_desc = { 89 .flags = LPSS_CLK, 90 }; 91 92 struct lpss_private_data { 93 struct acpi_device *adev; 94 void __iomem *mmio_base; 95 resource_size_t mmio_size; 96 unsigned int fixed_clk_rate; 97 struct clk *clk; 98 const struct lpss_device_desc *dev_desc; 99 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 100 }; 101 102 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 103 static u32 pmc_atom_d3_mask = 0xfe000ffe; 104 105 /* LPSS run time quirks */ 106 static unsigned int lpss_quirks; 107 108 /* 109 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 110 * 111 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 112 * it can be powered off automatically whenever the last LPSS device goes down. 113 * In case of no power any access to the DMA controller will hang the system. 114 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 115 * well as on ASuS T100TA transformer. 116 * 117 * This quirk overrides power state of entire LPSS island to keep DMA powered 118 * on whenever we have at least one other device in use. 119 */ 120 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 121 122 /* UART Component Parameter Register */ 123 #define LPSS_UART_CPR 0xF4 124 #define LPSS_UART_CPR_AFCE BIT(4) 125 126 static void lpss_uart_setup(struct lpss_private_data *pdata) 127 { 128 unsigned int offset; 129 u32 val; 130 131 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 132 val = readl(pdata->mmio_base + offset); 133 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 134 135 val = readl(pdata->mmio_base + LPSS_UART_CPR); 136 if (!(val & LPSS_UART_CPR_AFCE)) { 137 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 138 val = readl(pdata->mmio_base + offset); 139 val |= LPSS_GENERAL_UART_RTS_OVRD; 140 writel(val, pdata->mmio_base + offset); 141 } 142 } 143 144 static void lpss_deassert_reset(struct lpss_private_data *pdata) 145 { 146 unsigned int offset; 147 u32 val; 148 149 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 150 val = readl(pdata->mmio_base + offset); 151 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 152 writel(val, pdata->mmio_base + offset); 153 } 154 155 /* 156 * BYT PWM used for backlight control by the i915 driver on systems without 157 * the Crystal Cove PMIC. 158 */ 159 static struct pwm_lookup byt_pwm_lookup[] = { 160 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 161 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 162 "pwm-lpss-platform"), 163 }; 164 165 static void byt_pwm_setup(struct lpss_private_data *pdata) 166 { 167 struct acpi_device *adev = pdata->adev; 168 169 /* Only call pwm_add_table for the first PWM controller */ 170 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 171 return; 172 173 if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV)) 174 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 175 } 176 177 #define LPSS_I2C_ENABLE 0x6c 178 179 static void byt_i2c_setup(struct lpss_private_data *pdata) 180 { 181 const char *uid_str = acpi_device_uid(pdata->adev); 182 acpi_handle handle = pdata->adev->handle; 183 unsigned long long shared_host = 0; 184 acpi_status status; 185 long uid = 0; 186 187 /* Expected to always be true, but better safe then sorry */ 188 if (uid_str) 189 uid = simple_strtol(uid_str, NULL, 10); 190 191 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 192 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 193 if (ACPI_SUCCESS(status) && shared_host && uid) 194 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 195 196 lpss_deassert_reset(pdata); 197 198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 199 pdata->fixed_clk_rate = 133000000; 200 201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 202 } 203 204 /* BSW PWM used for backlight control by the i915 driver */ 205 static struct pwm_lookup bsw_pwm_lookup[] = { 206 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 207 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 208 "pwm-lpss-platform"), 209 }; 210 211 static void bsw_pwm_setup(struct lpss_private_data *pdata) 212 { 213 struct acpi_device *adev = pdata->adev; 214 215 /* Only call pwm_add_table for the first PWM controller */ 216 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 217 return; 218 219 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 220 } 221 222 static const struct lpss_device_desc lpt_dev_desc = { 223 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 224 | LPSS_SAVE_CTX, 225 .prv_offset = 0x800, 226 }; 227 228 static const struct lpss_device_desc lpt_i2c_dev_desc = { 229 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 230 .prv_offset = 0x800, 231 }; 232 233 static struct property_entry uart_properties[] = { 234 PROPERTY_ENTRY_U32("reg-io-width", 4), 235 PROPERTY_ENTRY_U32("reg-shift", 2), 236 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 237 { }, 238 }; 239 240 static const struct lpss_device_desc lpt_uart_dev_desc = { 241 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 242 | LPSS_SAVE_CTX, 243 .clk_con_id = "baudclk", 244 .prv_offset = 0x800, 245 .setup = lpss_uart_setup, 246 .properties = uart_properties, 247 }; 248 249 static const struct lpss_device_desc lpt_sdio_dev_desc = { 250 .flags = LPSS_LTR, 251 .prv_offset = 0x1000, 252 .prv_size_override = 0x1018, 253 }; 254 255 static const struct lpss_device_desc byt_pwm_dev_desc = { 256 .flags = LPSS_SAVE_CTX, 257 .prv_offset = 0x800, 258 .setup = byt_pwm_setup, 259 }; 260 261 static const struct lpss_device_desc bsw_pwm_dev_desc = { 262 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 263 .prv_offset = 0x800, 264 .setup = bsw_pwm_setup, 265 }; 266 267 static const struct lpss_device_desc byt_uart_dev_desc = { 268 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 269 .clk_con_id = "baudclk", 270 .prv_offset = 0x800, 271 .setup = lpss_uart_setup, 272 .properties = uart_properties, 273 }; 274 275 static const struct lpss_device_desc bsw_uart_dev_desc = { 276 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 277 | LPSS_NO_D3_DELAY, 278 .clk_con_id = "baudclk", 279 .prv_offset = 0x800, 280 .setup = lpss_uart_setup, 281 .properties = uart_properties, 282 }; 283 284 static const struct lpss_device_desc byt_spi_dev_desc = { 285 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 286 .prv_offset = 0x400, 287 }; 288 289 static const struct lpss_device_desc byt_sdio_dev_desc = { 290 .flags = LPSS_CLK, 291 }; 292 293 static const struct lpss_device_desc byt_i2c_dev_desc = { 294 .flags = LPSS_CLK | LPSS_SAVE_CTX, 295 .prv_offset = 0x800, 296 .setup = byt_i2c_setup, 297 .resume_from_noirq = true, 298 }; 299 300 static const struct lpss_device_desc bsw_i2c_dev_desc = { 301 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 302 .prv_offset = 0x800, 303 .setup = byt_i2c_setup, 304 .resume_from_noirq = true, 305 }; 306 307 static const struct lpss_device_desc bsw_spi_dev_desc = { 308 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 309 | LPSS_NO_D3_DELAY, 310 .prv_offset = 0x400, 311 .setup = lpss_deassert_reset, 312 }; 313 314 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } 315 316 static const struct x86_cpu_id lpss_cpu_ids[] = { 317 ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ 318 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ 319 {} 320 }; 321 322 #else 323 324 #define LPSS_ADDR(desc) (0UL) 325 326 #endif /* CONFIG_X86_INTEL_LPSS */ 327 328 static const struct acpi_device_id acpi_lpss_device_ids[] = { 329 /* Generic LPSS devices */ 330 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 331 332 /* Lynxpoint LPSS devices */ 333 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 334 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 335 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 336 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 337 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 338 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 339 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 340 { "INT33C7", }, 341 342 /* BayTrail LPSS devices */ 343 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 344 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 345 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 346 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 347 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 348 { "INT33B2", }, 349 { "INT33FC", }, 350 351 /* Braswell LPSS devices */ 352 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 353 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 354 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 355 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 356 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 357 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 358 359 /* Broadwell LPSS devices */ 360 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 361 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 362 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 363 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 364 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 365 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 366 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 367 { "INT3437", }, 368 369 /* Wildcat Point LPSS devices */ 370 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 371 372 { } 373 }; 374 375 #ifdef CONFIG_X86_INTEL_LPSS 376 377 static int is_memory(struct acpi_resource *res, void *not_used) 378 { 379 struct resource r; 380 return !acpi_dev_resource_memory(res, &r); 381 } 382 383 /* LPSS main clock device. */ 384 static struct platform_device *lpss_clk_dev; 385 386 static inline void lpt_register_clock_device(void) 387 { 388 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 389 } 390 391 static int register_device_clock(struct acpi_device *adev, 392 struct lpss_private_data *pdata) 393 { 394 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 395 const char *devname = dev_name(&adev->dev); 396 struct clk *clk; 397 struct lpss_clk_data *clk_data; 398 const char *parent, *clk_name; 399 void __iomem *prv_base; 400 401 if (!lpss_clk_dev) 402 lpt_register_clock_device(); 403 404 clk_data = platform_get_drvdata(lpss_clk_dev); 405 if (!clk_data) 406 return -ENODEV; 407 clk = clk_data->clk; 408 409 if (!pdata->mmio_base 410 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 411 return -ENODATA; 412 413 parent = clk_data->name; 414 prv_base = pdata->mmio_base + dev_desc->prv_offset; 415 416 if (pdata->fixed_clk_rate) { 417 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 418 pdata->fixed_clk_rate); 419 goto out; 420 } 421 422 if (dev_desc->flags & LPSS_CLK_GATE) { 423 clk = clk_register_gate(NULL, devname, parent, 0, 424 prv_base, 0, 0, NULL); 425 parent = devname; 426 } 427 428 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 429 /* Prevent division by zero */ 430 if (!readl(prv_base)) 431 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 432 433 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 434 if (!clk_name) 435 return -ENOMEM; 436 clk = clk_register_fractional_divider(NULL, clk_name, parent, 437 0, prv_base, 438 1, 15, 16, 15, 0, NULL); 439 parent = clk_name; 440 441 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 442 if (!clk_name) { 443 kfree(parent); 444 return -ENOMEM; 445 } 446 clk = clk_register_gate(NULL, clk_name, parent, 447 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 448 prv_base, 31, 0, NULL); 449 kfree(parent); 450 kfree(clk_name); 451 } 452 out: 453 if (IS_ERR(clk)) 454 return PTR_ERR(clk); 455 456 pdata->clk = clk; 457 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 458 return 0; 459 } 460 461 struct lpss_device_links { 462 const char *supplier_hid; 463 const char *supplier_uid; 464 const char *consumer_hid; 465 const char *consumer_uid; 466 u32 flags; 467 const struct dmi_system_id *dep_missing_ids; 468 }; 469 470 /* Please keep this list sorted alphabetically by vendor and model */ 471 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 472 { 473 .matches = { 474 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 475 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 476 }, 477 }, 478 {} 479 }; 480 481 /* 482 * The _DEP method is used to identify dependencies but instead of creating 483 * device links for every handle in _DEP, only links in the following list are 484 * created. That is necessary because, in the general case, _DEP can refer to 485 * devices that might not have drivers, or that are on different buses, or where 486 * the supplier is not enumerated until after the consumer is probed. 487 */ 488 static const struct lpss_device_links lpss_device_links[] = { 489 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 490 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 491 /* CHT iGPU depends on PMIC I2C controller */ 492 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 493 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 494 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 495 i2c1_dep_missing_dmi_ids}, 496 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 497 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 498 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 499 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 500 }; 501 502 static bool acpi_lpss_is_supplier(struct acpi_device *adev, 503 const struct lpss_device_links *link) 504 { 505 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 506 } 507 508 static bool acpi_lpss_is_consumer(struct acpi_device *adev, 509 const struct lpss_device_links *link) 510 { 511 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 512 } 513 514 struct hid_uid { 515 const char *hid; 516 const char *uid; 517 }; 518 519 static int match_hid_uid(struct device *dev, const void *data) 520 { 521 struct acpi_device *adev = ACPI_COMPANION(dev); 522 const struct hid_uid *id = data; 523 524 if (!adev) 525 return 0; 526 527 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 528 } 529 530 static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 531 { 532 struct device *dev; 533 534 struct hid_uid data = { 535 .hid = hid, 536 .uid = uid, 537 }; 538 539 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 540 if (dev) 541 return dev; 542 543 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 544 } 545 546 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 547 { 548 struct acpi_handle_list dep_devices; 549 acpi_status status; 550 int i; 551 552 if (!acpi_has_method(adev->handle, "_DEP")) 553 return false; 554 555 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 556 &dep_devices); 557 if (ACPI_FAILURE(status)) { 558 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 559 return false; 560 } 561 562 for (i = 0; i < dep_devices.count; i++) { 563 if (dep_devices.handles[i] == handle) 564 return true; 565 } 566 567 return false; 568 } 569 570 static void acpi_lpss_link_consumer(struct device *dev1, 571 const struct lpss_device_links *link) 572 { 573 struct device *dev2; 574 575 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 576 if (!dev2) 577 return; 578 579 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 580 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 581 device_link_add(dev2, dev1, link->flags); 582 583 put_device(dev2); 584 } 585 586 static void acpi_lpss_link_supplier(struct device *dev1, 587 const struct lpss_device_links *link) 588 { 589 struct device *dev2; 590 591 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 592 if (!dev2) 593 return; 594 595 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 596 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 597 device_link_add(dev1, dev2, link->flags); 598 599 put_device(dev2); 600 } 601 602 static void acpi_lpss_create_device_links(struct acpi_device *adev, 603 struct platform_device *pdev) 604 { 605 int i; 606 607 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 608 const struct lpss_device_links *link = &lpss_device_links[i]; 609 610 if (acpi_lpss_is_supplier(adev, link)) 611 acpi_lpss_link_consumer(&pdev->dev, link); 612 613 if (acpi_lpss_is_consumer(adev, link)) 614 acpi_lpss_link_supplier(&pdev->dev, link); 615 } 616 } 617 618 static int acpi_lpss_create_device(struct acpi_device *adev, 619 const struct acpi_device_id *id) 620 { 621 const struct lpss_device_desc *dev_desc; 622 struct lpss_private_data *pdata; 623 struct resource_entry *rentry; 624 struct list_head resource_list; 625 struct platform_device *pdev; 626 int ret; 627 628 dev_desc = (const struct lpss_device_desc *)id->driver_data; 629 if (!dev_desc) { 630 pdev = acpi_create_platform_device(adev, NULL); 631 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 632 } 633 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 634 if (!pdata) 635 return -ENOMEM; 636 637 INIT_LIST_HEAD(&resource_list); 638 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 639 if (ret < 0) 640 goto err_out; 641 642 list_for_each_entry(rentry, &resource_list, node) 643 if (resource_type(rentry->res) == IORESOURCE_MEM) { 644 if (dev_desc->prv_size_override) 645 pdata->mmio_size = dev_desc->prv_size_override; 646 else 647 pdata->mmio_size = resource_size(rentry->res); 648 pdata->mmio_base = ioremap(rentry->res->start, 649 pdata->mmio_size); 650 break; 651 } 652 653 acpi_dev_free_resource_list(&resource_list); 654 655 if (!pdata->mmio_base) { 656 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 657 adev->pnp.type.platform_id = 0; 658 /* Skip the device, but continue the namespace scan. */ 659 ret = 0; 660 goto err_out; 661 } 662 663 pdata->adev = adev; 664 pdata->dev_desc = dev_desc; 665 666 if (dev_desc->setup) 667 dev_desc->setup(pdata); 668 669 if (dev_desc->flags & LPSS_CLK) { 670 ret = register_device_clock(adev, pdata); 671 if (ret) { 672 /* Skip the device, but continue the namespace scan. */ 673 ret = 0; 674 goto err_out; 675 } 676 } 677 678 /* 679 * This works around a known issue in ACPI tables where LPSS devices 680 * have _PS0 and _PS3 without _PSC (and no power resources), so 681 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 682 */ 683 acpi_device_fix_up_power(adev); 684 685 adev->driver_data = pdata; 686 pdev = acpi_create_platform_device(adev, dev_desc->properties); 687 if (!IS_ERR_OR_NULL(pdev)) { 688 acpi_lpss_create_device_links(adev, pdev); 689 return 1; 690 } 691 692 ret = PTR_ERR(pdev); 693 adev->driver_data = NULL; 694 695 err_out: 696 kfree(pdata); 697 return ret; 698 } 699 700 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 701 { 702 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 703 } 704 705 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 706 unsigned int reg) 707 { 708 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 709 } 710 711 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 712 { 713 struct acpi_device *adev; 714 struct lpss_private_data *pdata; 715 unsigned long flags; 716 int ret; 717 718 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 719 if (WARN_ON(ret)) 720 return ret; 721 722 spin_lock_irqsave(&dev->power.lock, flags); 723 if (pm_runtime_suspended(dev)) { 724 ret = -EAGAIN; 725 goto out; 726 } 727 pdata = acpi_driver_data(adev); 728 if (WARN_ON(!pdata || !pdata->mmio_base)) { 729 ret = -ENODEV; 730 goto out; 731 } 732 *val = __lpss_reg_read(pdata, reg); 733 734 out: 735 spin_unlock_irqrestore(&dev->power.lock, flags); 736 return ret; 737 } 738 739 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 740 char *buf) 741 { 742 u32 ltr_value = 0; 743 unsigned int reg; 744 int ret; 745 746 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 747 ret = lpss_reg_read(dev, reg, <r_value); 748 if (ret) 749 return ret; 750 751 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 752 } 753 754 static ssize_t lpss_ltr_mode_show(struct device *dev, 755 struct device_attribute *attr, char *buf) 756 { 757 u32 ltr_mode = 0; 758 char *outstr; 759 int ret; 760 761 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 762 if (ret) 763 return ret; 764 765 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 766 return sprintf(buf, "%s\n", outstr); 767 } 768 769 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 770 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 771 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 772 773 static struct attribute *lpss_attrs[] = { 774 &dev_attr_auto_ltr.attr, 775 &dev_attr_sw_ltr.attr, 776 &dev_attr_ltr_mode.attr, 777 NULL, 778 }; 779 780 static const struct attribute_group lpss_attr_group = { 781 .attrs = lpss_attrs, 782 .name = "lpss_ltr", 783 }; 784 785 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 786 { 787 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 788 u32 ltr_mode, ltr_val; 789 790 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 791 if (val < 0) { 792 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 793 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 794 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 795 } 796 return; 797 } 798 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 799 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 800 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 801 val = LPSS_LTR_MAX_VAL; 802 } else if (val > LPSS_LTR_MAX_VAL) { 803 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 804 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 805 } else { 806 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 807 } 808 ltr_val |= val; 809 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 810 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 811 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 812 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 813 } 814 } 815 816 #ifdef CONFIG_PM 817 /** 818 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 819 * @dev: LPSS device 820 * @pdata: pointer to the private data of the LPSS device 821 * 822 * Most LPSS devices have private registers which may loose their context when 823 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 824 * prv_reg_ctx array. 825 */ 826 static void acpi_lpss_save_ctx(struct device *dev, 827 struct lpss_private_data *pdata) 828 { 829 unsigned int i; 830 831 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 832 unsigned long offset = i * sizeof(u32); 833 834 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 835 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 836 pdata->prv_reg_ctx[i], offset); 837 } 838 } 839 840 /** 841 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 842 * @dev: LPSS device 843 * @pdata: pointer to the private data of the LPSS device 844 * 845 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 846 */ 847 static void acpi_lpss_restore_ctx(struct device *dev, 848 struct lpss_private_data *pdata) 849 { 850 unsigned int i; 851 852 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 853 unsigned long offset = i * sizeof(u32); 854 855 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 856 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 857 pdata->prv_reg_ctx[i], offset); 858 } 859 } 860 861 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 862 { 863 /* 864 * The following delay is needed or the subsequent write operations may 865 * fail. The LPSS devices are actually PCI devices and the PCI spec 866 * expects 10ms delay before the device can be accessed after D3 to D0 867 * transition. However some platforms like BSW does not need this delay. 868 */ 869 unsigned int delay = 10; /* default 10ms delay */ 870 871 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 872 delay = 0; 873 874 msleep(delay); 875 } 876 877 static int acpi_lpss_activate(struct device *dev) 878 { 879 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 880 int ret; 881 882 ret = acpi_dev_resume(dev); 883 if (ret) 884 return ret; 885 886 acpi_lpss_d3_to_d0_delay(pdata); 887 888 /* 889 * This is called only on ->probe() stage where a device is either in 890 * known state defined by BIOS or most likely powered off. Due to this 891 * we have to deassert reset line to be sure that ->probe() will 892 * recognize the device. 893 */ 894 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 895 lpss_deassert_reset(pdata); 896 897 return 0; 898 } 899 900 static void acpi_lpss_dismiss(struct device *dev) 901 { 902 acpi_dev_suspend(dev, false); 903 } 904 905 /* IOSF SB for LPSS island */ 906 #define LPSS_IOSF_UNIT_LPIOEP 0xA0 907 #define LPSS_IOSF_UNIT_LPIO1 0xAB 908 #define LPSS_IOSF_UNIT_LPIO2 0xAC 909 910 #define LPSS_IOSF_PMCSR 0x84 911 #define LPSS_PMCSR_D0 0 912 #define LPSS_PMCSR_D3hot 3 913 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 914 915 #define LPSS_IOSF_GPIODEF0 0x154 916 #define LPSS_GPIODEF0_DMA1_D3 BIT(2) 917 #define LPSS_GPIODEF0_DMA2_D3 BIT(3) 918 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 919 #define LPSS_GPIODEF0_DMA_LLP BIT(13) 920 921 static DEFINE_MUTEX(lpss_iosf_mutex); 922 static bool lpss_iosf_d3_entered = true; 923 924 static void lpss_iosf_enter_d3_state(void) 925 { 926 u32 value1 = 0; 927 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 928 u32 value2 = LPSS_PMCSR_D3hot; 929 u32 mask2 = LPSS_PMCSR_Dx_MASK; 930 /* 931 * PMC provides an information about actual status of the LPSS devices. 932 * Here we read the values related to LPSS power island, i.e. LPSS 933 * devices, excluding both LPSS DMA controllers, along with SCC domain. 934 */ 935 u32 func_dis, d3_sts_0, pmc_status; 936 int ret; 937 938 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 939 if (ret) 940 return; 941 942 mutex_lock(&lpss_iosf_mutex); 943 944 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 945 if (ret) 946 goto exit; 947 948 /* 949 * Get the status of entire LPSS power island per device basis. 950 * Shutdown both LPSS DMA controllers if and only if all other devices 951 * are already in D3hot. 952 */ 953 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 954 if (pmc_status) 955 goto exit; 956 957 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 958 LPSS_IOSF_PMCSR, value2, mask2); 959 960 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 961 LPSS_IOSF_PMCSR, value2, mask2); 962 963 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 964 LPSS_IOSF_GPIODEF0, value1, mask1); 965 966 lpss_iosf_d3_entered = true; 967 968 exit: 969 mutex_unlock(&lpss_iosf_mutex); 970 } 971 972 static void lpss_iosf_exit_d3_state(void) 973 { 974 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 975 LPSS_GPIODEF0_DMA_LLP; 976 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 977 u32 value2 = LPSS_PMCSR_D0; 978 u32 mask2 = LPSS_PMCSR_Dx_MASK; 979 980 mutex_lock(&lpss_iosf_mutex); 981 982 if (!lpss_iosf_d3_entered) 983 goto exit; 984 985 lpss_iosf_d3_entered = false; 986 987 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 988 LPSS_IOSF_GPIODEF0, value1, mask1); 989 990 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 991 LPSS_IOSF_PMCSR, value2, mask2); 992 993 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 994 LPSS_IOSF_PMCSR, value2, mask2); 995 996 exit: 997 mutex_unlock(&lpss_iosf_mutex); 998 } 999 1000 static int acpi_lpss_suspend(struct device *dev, bool wakeup) 1001 { 1002 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1003 int ret; 1004 1005 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1006 acpi_lpss_save_ctx(dev, pdata); 1007 1008 ret = acpi_dev_suspend(dev, wakeup); 1009 1010 /* 1011 * This call must be last in the sequence, otherwise PMC will return 1012 * wrong status for devices being about to be powered off. See 1013 * lpss_iosf_enter_d3_state() for further information. 1014 */ 1015 if (acpi_target_system_state() == ACPI_STATE_S0 && 1016 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1017 lpss_iosf_enter_d3_state(); 1018 1019 return ret; 1020 } 1021 1022 static int acpi_lpss_resume(struct device *dev) 1023 { 1024 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1025 int ret; 1026 1027 /* 1028 * This call is kept first to be in symmetry with 1029 * acpi_lpss_runtime_suspend() one. 1030 */ 1031 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1032 lpss_iosf_exit_d3_state(); 1033 1034 ret = acpi_dev_resume(dev); 1035 if (ret) 1036 return ret; 1037 1038 acpi_lpss_d3_to_d0_delay(pdata); 1039 1040 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1041 acpi_lpss_restore_ctx(dev, pdata); 1042 1043 return 0; 1044 } 1045 1046 #ifdef CONFIG_PM_SLEEP 1047 static int acpi_lpss_do_suspend_late(struct device *dev) 1048 { 1049 int ret; 1050 1051 if (dev_pm_smart_suspend_and_suspended(dev)) 1052 return 0; 1053 1054 ret = pm_generic_suspend_late(dev); 1055 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1056 } 1057 1058 static int acpi_lpss_suspend_late(struct device *dev) 1059 { 1060 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1061 1062 if (pdata->dev_desc->resume_from_noirq) 1063 return 0; 1064 1065 return acpi_lpss_do_suspend_late(dev); 1066 } 1067 1068 static int acpi_lpss_suspend_noirq(struct device *dev) 1069 { 1070 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1071 int ret; 1072 1073 if (pdata->dev_desc->resume_from_noirq) { 1074 /* 1075 * The driver's ->suspend_late callback will be invoked by 1076 * acpi_lpss_do_suspend_late(), with the assumption that the 1077 * driver really wanted to run that code in ->suspend_noirq, but 1078 * it could not run after acpi_dev_suspend() and the driver 1079 * expected the latter to be called in the "late" phase. 1080 */ 1081 ret = acpi_lpss_do_suspend_late(dev); 1082 if (ret) 1083 return ret; 1084 } 1085 1086 return acpi_subsys_suspend_noirq(dev); 1087 } 1088 1089 static int acpi_lpss_do_resume_early(struct device *dev) 1090 { 1091 int ret = acpi_lpss_resume(dev); 1092 1093 return ret ? ret : pm_generic_resume_early(dev); 1094 } 1095 1096 static int acpi_lpss_resume_early(struct device *dev) 1097 { 1098 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1099 1100 if (pdata->dev_desc->resume_from_noirq) 1101 return 0; 1102 1103 return acpi_lpss_do_resume_early(dev); 1104 } 1105 1106 static int acpi_lpss_resume_noirq(struct device *dev) 1107 { 1108 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1109 int ret; 1110 1111 /* Follow acpi_subsys_resume_noirq(). */ 1112 if (dev_pm_may_skip_resume(dev)) 1113 return 0; 1114 1115 if (dev_pm_smart_suspend_and_suspended(dev)) 1116 pm_runtime_set_active(dev); 1117 1118 ret = pm_generic_resume_noirq(dev); 1119 if (ret) 1120 return ret; 1121 1122 if (!pdata->dev_desc->resume_from_noirq) 1123 return 0; 1124 1125 /* 1126 * The driver's ->resume_early callback will be invoked by 1127 * acpi_lpss_do_resume_early(), with the assumption that the driver 1128 * really wanted to run that code in ->resume_noirq, but it could not 1129 * run before acpi_dev_resume() and the driver expected the latter to be 1130 * called in the "early" phase. 1131 */ 1132 return acpi_lpss_do_resume_early(dev); 1133 } 1134 1135 static int acpi_lpss_do_restore_early(struct device *dev) 1136 { 1137 int ret = acpi_lpss_resume(dev); 1138 1139 return ret ? ret : pm_generic_restore_early(dev); 1140 } 1141 1142 static int acpi_lpss_restore_early(struct device *dev) 1143 { 1144 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1145 1146 if (pdata->dev_desc->resume_from_noirq) 1147 return 0; 1148 1149 return acpi_lpss_do_restore_early(dev); 1150 } 1151 1152 static int acpi_lpss_restore_noirq(struct device *dev) 1153 { 1154 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1155 int ret; 1156 1157 ret = pm_generic_restore_noirq(dev); 1158 if (ret) 1159 return ret; 1160 1161 if (!pdata->dev_desc->resume_from_noirq) 1162 return 0; 1163 1164 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1165 return acpi_lpss_do_restore_early(dev); 1166 } 1167 1168 static int acpi_lpss_do_poweroff_late(struct device *dev) 1169 { 1170 int ret = pm_generic_poweroff_late(dev); 1171 1172 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1173 } 1174 1175 static int acpi_lpss_poweroff_late(struct device *dev) 1176 { 1177 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1178 1179 if (dev_pm_smart_suspend_and_suspended(dev)) 1180 return 0; 1181 1182 if (pdata->dev_desc->resume_from_noirq) 1183 return 0; 1184 1185 return acpi_lpss_do_poweroff_late(dev); 1186 } 1187 1188 static int acpi_lpss_poweroff_noirq(struct device *dev) 1189 { 1190 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1191 1192 if (dev_pm_smart_suspend_and_suspended(dev)) 1193 return 0; 1194 1195 if (pdata->dev_desc->resume_from_noirq) { 1196 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1197 int ret = acpi_lpss_do_poweroff_late(dev); 1198 if (ret) 1199 return ret; 1200 } 1201 1202 return pm_generic_poweroff_noirq(dev); 1203 } 1204 #endif /* CONFIG_PM_SLEEP */ 1205 1206 static int acpi_lpss_runtime_suspend(struct device *dev) 1207 { 1208 int ret = pm_generic_runtime_suspend(dev); 1209 1210 return ret ? ret : acpi_lpss_suspend(dev, true); 1211 } 1212 1213 static int acpi_lpss_runtime_resume(struct device *dev) 1214 { 1215 int ret = acpi_lpss_resume(dev); 1216 1217 return ret ? ret : pm_generic_runtime_resume(dev); 1218 } 1219 #endif /* CONFIG_PM */ 1220 1221 static struct dev_pm_domain acpi_lpss_pm_domain = { 1222 #ifdef CONFIG_PM 1223 .activate = acpi_lpss_activate, 1224 .dismiss = acpi_lpss_dismiss, 1225 #endif 1226 .ops = { 1227 #ifdef CONFIG_PM 1228 #ifdef CONFIG_PM_SLEEP 1229 .prepare = acpi_subsys_prepare, 1230 .complete = acpi_subsys_complete, 1231 .suspend = acpi_subsys_suspend, 1232 .suspend_late = acpi_lpss_suspend_late, 1233 .suspend_noirq = acpi_lpss_suspend_noirq, 1234 .resume_noirq = acpi_lpss_resume_noirq, 1235 .resume_early = acpi_lpss_resume_early, 1236 .freeze = acpi_subsys_freeze, 1237 .poweroff = acpi_subsys_poweroff, 1238 .poweroff_late = acpi_lpss_poweroff_late, 1239 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1240 .restore_noirq = acpi_lpss_restore_noirq, 1241 .restore_early = acpi_lpss_restore_early, 1242 #endif 1243 .runtime_suspend = acpi_lpss_runtime_suspend, 1244 .runtime_resume = acpi_lpss_runtime_resume, 1245 #endif 1246 }, 1247 }; 1248 1249 static int acpi_lpss_platform_notify(struct notifier_block *nb, 1250 unsigned long action, void *data) 1251 { 1252 struct platform_device *pdev = to_platform_device(data); 1253 struct lpss_private_data *pdata; 1254 struct acpi_device *adev; 1255 const struct acpi_device_id *id; 1256 1257 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1258 if (!id || !id->driver_data) 1259 return 0; 1260 1261 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1262 return 0; 1263 1264 pdata = acpi_driver_data(adev); 1265 if (!pdata) 1266 return 0; 1267 1268 if (pdata->mmio_base && 1269 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1270 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1271 return 0; 1272 } 1273 1274 switch (action) { 1275 case BUS_NOTIFY_BIND_DRIVER: 1276 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1277 break; 1278 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1279 case BUS_NOTIFY_UNBOUND_DRIVER: 1280 dev_pm_domain_set(&pdev->dev, NULL); 1281 break; 1282 case BUS_NOTIFY_ADD_DEVICE: 1283 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1284 if (pdata->dev_desc->flags & LPSS_LTR) 1285 return sysfs_create_group(&pdev->dev.kobj, 1286 &lpss_attr_group); 1287 break; 1288 case BUS_NOTIFY_DEL_DEVICE: 1289 if (pdata->dev_desc->flags & LPSS_LTR) 1290 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1291 dev_pm_domain_set(&pdev->dev, NULL); 1292 break; 1293 default: 1294 break; 1295 } 1296 1297 return 0; 1298 } 1299 1300 static struct notifier_block acpi_lpss_nb = { 1301 .notifier_call = acpi_lpss_platform_notify, 1302 }; 1303 1304 static void acpi_lpss_bind(struct device *dev) 1305 { 1306 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1307 1308 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1309 return; 1310 1311 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1312 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1313 else 1314 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1315 } 1316 1317 static void acpi_lpss_unbind(struct device *dev) 1318 { 1319 dev->power.set_latency_tolerance = NULL; 1320 } 1321 1322 static struct acpi_scan_handler lpss_handler = { 1323 .ids = acpi_lpss_device_ids, 1324 .attach = acpi_lpss_create_device, 1325 .bind = acpi_lpss_bind, 1326 .unbind = acpi_lpss_unbind, 1327 }; 1328 1329 void __init acpi_lpss_init(void) 1330 { 1331 const struct x86_cpu_id *id; 1332 int ret; 1333 1334 ret = lpt_clk_init(); 1335 if (ret) 1336 return; 1337 1338 id = x86_match_cpu(lpss_cpu_ids); 1339 if (id) 1340 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1341 1342 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1343 acpi_scan_add_handler(&lpss_handler); 1344 } 1345 1346 #else 1347 1348 static struct acpi_scan_handler lpss_handler = { 1349 .ids = acpi_lpss_device_ids, 1350 }; 1351 1352 void __init acpi_lpss_init(void) 1353 { 1354 acpi_scan_add_handler(&lpss_handler); 1355 } 1356 1357 #endif /* CONFIG_X86_INTEL_LPSS */ 1358