xref: /openbmc/linux/drivers/acpi/acpi_lpss.c (revision 6db6b729)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * ACPI support for Intel Lynxpoint LPSS.
4  *
5  * Copyright (C) 2013, Intel Corporation
6  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/pxa2xx_ssp.h>
25 #include <linux/suspend.h>
26 #include <linux/delay.h>
27 
28 #include "internal.h"
29 
30 #ifdef CONFIG_X86_INTEL_LPSS
31 
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
35 
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
37 
38 #define LPSS_CLK_SIZE	0x04
39 #define LPSS_LTR_SIZE	0x18
40 
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK	(BIT(1) | BIT(16))
43 #define LPSS_RESETS			0x04
44 #define LPSS_RESETS_RESET_FUNC		BIT(0)
45 #define LPSS_RESETS_RESET_APB		BIT(1)
46 #define LPSS_GENERAL			0x08
47 #define LPSS_GENERAL_LTR_MODE_SW	BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD	BIT(3)
49 #define LPSS_SW_LTR			0x10
50 #define LPSS_AUTO_LTR			0x14
51 #define LPSS_LTR_SNOOP_REQ		BIT(15)
52 #define LPSS_LTR_SNOOP_MASK		0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US		0x800
54 #define LPSS_LTR_SNOOP_LAT_32US		0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT	5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF	3000
57 #define LPSS_LTR_MAX_VAL		0x3FF
58 #define LPSS_TX_INT			0x20
59 #define LPSS_TX_INT_MASK		BIT(1)
60 
61 #define LPSS_PRV_REG_COUNT		9
62 
63 /* LPSS Flags */
64 #define LPSS_CLK			BIT(0)
65 #define LPSS_CLK_GATE			BIT(1)
66 #define LPSS_CLK_DIVIDER		BIT(2)
67 #define LPSS_LTR			BIT(3)
68 #define LPSS_SAVE_CTX			BIT(4)
69 /*
70  * For some devices the DSDT AML code for another device turns off the device
71  * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
72  * as ctx register values.
73  * Luckily these devices always use the same ctx register values, so we can
74  * work around this by saving the ctx registers once on activation.
75  */
76 #define LPSS_SAVE_CTX_ONCE		BIT(5)
77 #define LPSS_NO_D3_DELAY		BIT(6)
78 
79 struct lpss_private_data;
80 
81 struct lpss_device_desc {
82 	unsigned int flags;
83 	const char *clk_con_id;
84 	unsigned int prv_offset;
85 	size_t prv_size_override;
86 	const struct property_entry *properties;
87 	void (*setup)(struct lpss_private_data *pdata);
88 	bool resume_from_noirq;
89 };
90 
91 static const struct lpss_device_desc lpss_dma_desc = {
92 	.flags = LPSS_CLK,
93 };
94 
95 struct lpss_private_data {
96 	struct acpi_device *adev;
97 	void __iomem *mmio_base;
98 	resource_size_t mmio_size;
99 	unsigned int fixed_clk_rate;
100 	struct clk *clk;
101 	const struct lpss_device_desc *dev_desc;
102 	u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
103 };
104 
105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
107 
108 /* LPSS run time quirks */
109 static unsigned int lpss_quirks;
110 
111 /*
112  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
113  *
114  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
115  * it can be powered off automatically whenever the last LPSS device goes down.
116  * In case of no power any access to the DMA controller will hang the system.
117  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
118  * well as on ASuS T100TA transformer.
119  *
120  * This quirk overrides power state of entire LPSS island to keep DMA powered
121  * on whenever we have at least one other device in use.
122  */
123 #define LPSS_QUIRK_ALWAYS_POWER_ON	BIT(0)
124 
125 /* UART Component Parameter Register */
126 #define LPSS_UART_CPR			0xF4
127 #define LPSS_UART_CPR_AFCE		BIT(4)
128 
129 static void lpss_uart_setup(struct lpss_private_data *pdata)
130 {
131 	unsigned int offset;
132 	u32 val;
133 
134 	offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
135 	val = readl(pdata->mmio_base + offset);
136 	writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
137 
138 	val = readl(pdata->mmio_base + LPSS_UART_CPR);
139 	if (!(val & LPSS_UART_CPR_AFCE)) {
140 		offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
141 		val = readl(pdata->mmio_base + offset);
142 		val |= LPSS_GENERAL_UART_RTS_OVRD;
143 		writel(val, pdata->mmio_base + offset);
144 	}
145 }
146 
147 static void lpss_deassert_reset(struct lpss_private_data *pdata)
148 {
149 	unsigned int offset;
150 	u32 val;
151 
152 	offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
153 	val = readl(pdata->mmio_base + offset);
154 	val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
155 	writel(val, pdata->mmio_base + offset);
156 }
157 
158 /*
159  * BYT PWM used for backlight control by the i915 driver on systems without
160  * the Crystal Cove PMIC.
161  */
162 static struct pwm_lookup byt_pwm_lookup[] = {
163 	PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
164 			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
165 			       "pwm-lpss-platform"),
166 };
167 
168 static void byt_pwm_setup(struct lpss_private_data *pdata)
169 {
170 	u64 uid;
171 
172 	/* Only call pwm_add_table for the first PWM controller */
173 	if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
174 		return;
175 
176 	pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
177 }
178 
179 #define LPSS_I2C_ENABLE			0x6c
180 
181 static void byt_i2c_setup(struct lpss_private_data *pdata)
182 {
183 	acpi_handle handle = pdata->adev->handle;
184 	unsigned long long shared_host = 0;
185 	acpi_status status;
186 	u64 uid;
187 
188 	/* Expected to always be successfull, but better safe then sorry */
189 	if (!acpi_dev_uid_to_integer(pdata->adev, &uid) && uid) {
190 		/* Detect I2C bus shared with PUNIT and ignore its d3 status */
191 		status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
192 		if (ACPI_SUCCESS(status) && shared_host)
193 			pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
194 	}
195 
196 	lpss_deassert_reset(pdata);
197 
198 	if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
199 		pdata->fixed_clk_rate = 133000000;
200 
201 	writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
202 }
203 
204 /*
205  * BSW PWM1 is used for backlight control by the i915 driver
206  * BSW PWM2 is used for backlight control for fixed (etched into the glass)
207  * touch controls on some models. These touch-controls have specialized
208  * drivers which know they need the "pwm_soc_lpss_2" con-id.
209  */
210 static struct pwm_lookup bsw_pwm_lookup[] = {
211 	PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
212 			       "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
213 			       "pwm-lpss-platform"),
214 	PWM_LOOKUP_WITH_MODULE("80862289:00", 0, NULL,
215 			       "pwm_soc_lpss_2", 0, PWM_POLARITY_NORMAL,
216 			       "pwm-lpss-platform"),
217 };
218 
219 static void bsw_pwm_setup(struct lpss_private_data *pdata)
220 {
221 	u64 uid;
222 
223 	/* Only call pwm_add_table for the first PWM controller */
224 	if (acpi_dev_uid_to_integer(pdata->adev, &uid) || uid != 1)
225 		return;
226 
227 	pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
228 }
229 
230 static const struct property_entry lpt_spi_properties[] = {
231 	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
232 	{ }
233 };
234 
235 static const struct lpss_device_desc lpt_spi_dev_desc = {
236 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
237 			| LPSS_SAVE_CTX,
238 	.prv_offset = 0x800,
239 	.properties = lpt_spi_properties,
240 };
241 
242 static const struct lpss_device_desc lpt_i2c_dev_desc = {
243 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
244 	.prv_offset = 0x800,
245 };
246 
247 static struct property_entry uart_properties[] = {
248 	PROPERTY_ENTRY_U32("reg-io-width", 4),
249 	PROPERTY_ENTRY_U32("reg-shift", 2),
250 	PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
251 	{ },
252 };
253 
254 static const struct lpss_device_desc lpt_uart_dev_desc = {
255 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
256 			| LPSS_SAVE_CTX,
257 	.clk_con_id = "baudclk",
258 	.prv_offset = 0x800,
259 	.setup = lpss_uart_setup,
260 	.properties = uart_properties,
261 };
262 
263 static const struct lpss_device_desc lpt_sdio_dev_desc = {
264 	.flags = LPSS_LTR,
265 	.prv_offset = 0x1000,
266 	.prv_size_override = 0x1018,
267 };
268 
269 static const struct lpss_device_desc byt_pwm_dev_desc = {
270 	.flags = LPSS_SAVE_CTX,
271 	.prv_offset = 0x800,
272 	.setup = byt_pwm_setup,
273 };
274 
275 static const struct lpss_device_desc bsw_pwm_dev_desc = {
276 	.flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
277 	.prv_offset = 0x800,
278 	.setup = bsw_pwm_setup,
279 	.resume_from_noirq = true,
280 };
281 
282 static const struct lpss_device_desc bsw_pwm2_dev_desc = {
283 	.flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
284 	.prv_offset = 0x800,
285 	.resume_from_noirq = true,
286 };
287 
288 static const struct lpss_device_desc byt_uart_dev_desc = {
289 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
290 	.clk_con_id = "baudclk",
291 	.prv_offset = 0x800,
292 	.setup = lpss_uart_setup,
293 	.properties = uart_properties,
294 };
295 
296 static const struct lpss_device_desc bsw_uart_dev_desc = {
297 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
298 			| LPSS_NO_D3_DELAY,
299 	.clk_con_id = "baudclk",
300 	.prv_offset = 0x800,
301 	.setup = lpss_uart_setup,
302 	.properties = uart_properties,
303 };
304 
305 static const struct property_entry byt_spi_properties[] = {
306 	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
307 	{ }
308 };
309 
310 static const struct lpss_device_desc byt_spi_dev_desc = {
311 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
312 	.prv_offset = 0x400,
313 	.properties = byt_spi_properties,
314 };
315 
316 static const struct lpss_device_desc byt_sdio_dev_desc = {
317 	.flags = LPSS_CLK,
318 };
319 
320 static const struct lpss_device_desc byt_i2c_dev_desc = {
321 	.flags = LPSS_CLK | LPSS_SAVE_CTX,
322 	.prv_offset = 0x800,
323 	.setup = byt_i2c_setup,
324 	.resume_from_noirq = true,
325 };
326 
327 static const struct lpss_device_desc bsw_i2c_dev_desc = {
328 	.flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
329 	.prv_offset = 0x800,
330 	.setup = byt_i2c_setup,
331 	.resume_from_noirq = true,
332 };
333 
334 static const struct property_entry bsw_spi_properties[] = {
335 	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
336 	{ }
337 };
338 
339 static const struct lpss_device_desc bsw_spi_dev_desc = {
340 	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
341 			| LPSS_NO_D3_DELAY,
342 	.prv_offset = 0x400,
343 	.setup = lpss_deassert_reset,
344 	.properties = bsw_spi_properties,
345 };
346 
347 static const struct x86_cpu_id lpss_cpu_ids[] = {
348 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT,	NULL),
349 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,	NULL),
350 	{}
351 };
352 
353 #else
354 
355 #define LPSS_ADDR(desc) (0UL)
356 
357 #endif /* CONFIG_X86_INTEL_LPSS */
358 
359 static const struct acpi_device_id acpi_lpss_device_ids[] = {
360 	/* Generic LPSS devices */
361 	{ "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
362 
363 	/* Lynxpoint LPSS devices */
364 	{ "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
365 	{ "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
366 	{ "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
367 	{ "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
368 	{ "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
369 	{ "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
370 	{ "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
371 	{ "INT33C7", },
372 
373 	/* BayTrail LPSS devices */
374 	{ "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
375 	{ "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
376 	{ "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
377 	{ "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
378 	{ "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
379 	{ "INT33B2", },
380 	{ "INT33FC", },
381 
382 	/* Braswell LPSS devices */
383 	{ "80862286", LPSS_ADDR(lpss_dma_desc) },
384 	{ "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
385 	{ "80862289", LPSS_ADDR(bsw_pwm2_dev_desc) },
386 	{ "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
387 	{ "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
388 	{ "808622C0", LPSS_ADDR(lpss_dma_desc) },
389 	{ "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
390 
391 	/* Broadwell LPSS devices */
392 	{ "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
393 	{ "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
394 	{ "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
395 	{ "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
396 	{ "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
397 	{ "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
398 	{ "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
399 	{ "INT3437", },
400 
401 	/* Wildcat Point LPSS devices */
402 	{ "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
403 
404 	{ }
405 };
406 
407 #ifdef CONFIG_X86_INTEL_LPSS
408 
409 /* LPSS main clock device. */
410 static struct platform_device *lpss_clk_dev;
411 
412 static inline void lpt_register_clock_device(void)
413 {
414 	lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
415 						       PLATFORM_DEVID_NONE,
416 						       NULL, 0);
417 }
418 
419 static int register_device_clock(struct acpi_device *adev,
420 				 struct lpss_private_data *pdata)
421 {
422 	const struct lpss_device_desc *dev_desc = pdata->dev_desc;
423 	const char *devname = dev_name(&adev->dev);
424 	struct clk *clk;
425 	struct lpss_clk_data *clk_data;
426 	const char *parent, *clk_name;
427 	void __iomem *prv_base;
428 
429 	if (!lpss_clk_dev)
430 		lpt_register_clock_device();
431 
432 	if (IS_ERR(lpss_clk_dev))
433 		return PTR_ERR(lpss_clk_dev);
434 
435 	clk_data = platform_get_drvdata(lpss_clk_dev);
436 	if (!clk_data)
437 		return -ENODEV;
438 	clk = clk_data->clk;
439 
440 	if (!pdata->mmio_base
441 	    || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
442 		return -ENODATA;
443 
444 	parent = clk_data->name;
445 	prv_base = pdata->mmio_base + dev_desc->prv_offset;
446 
447 	if (pdata->fixed_clk_rate) {
448 		clk = clk_register_fixed_rate(NULL, devname, parent, 0,
449 					      pdata->fixed_clk_rate);
450 		goto out;
451 	}
452 
453 	if (dev_desc->flags & LPSS_CLK_GATE) {
454 		clk = clk_register_gate(NULL, devname, parent, 0,
455 					prv_base, 0, 0, NULL);
456 		parent = devname;
457 	}
458 
459 	if (dev_desc->flags & LPSS_CLK_DIVIDER) {
460 		/* Prevent division by zero */
461 		if (!readl(prv_base))
462 			writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
463 
464 		clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
465 		if (!clk_name)
466 			return -ENOMEM;
467 		clk = clk_register_fractional_divider(NULL, clk_name, parent,
468 						      CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
469 						      prv_base, 1, 15, 16, 15, 0, NULL);
470 		parent = clk_name;
471 
472 		clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
473 		if (!clk_name) {
474 			kfree(parent);
475 			return -ENOMEM;
476 		}
477 		clk = clk_register_gate(NULL, clk_name, parent,
478 					CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
479 					prv_base, 31, 0, NULL);
480 		kfree(parent);
481 		kfree(clk_name);
482 	}
483 out:
484 	if (IS_ERR(clk))
485 		return PTR_ERR(clk);
486 
487 	pdata->clk = clk;
488 	clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
489 	return 0;
490 }
491 
492 struct lpss_device_links {
493 	const char *supplier_hid;
494 	const char *supplier_uid;
495 	const char *consumer_hid;
496 	const char *consumer_uid;
497 	u32 flags;
498 	const struct dmi_system_id *dep_missing_ids;
499 };
500 
501 /* Please keep this list sorted alphabetically by vendor and model */
502 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
503 	{
504 		.matches = {
505 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
506 			DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
507 		},
508 	},
509 	{}
510 };
511 
512 /*
513  * The _DEP method is used to identify dependencies but instead of creating
514  * device links for every handle in _DEP, only links in the following list are
515  * created. That is necessary because, in the general case, _DEP can refer to
516  * devices that might not have drivers, or that are on different buses, or where
517  * the supplier is not enumerated until after the consumer is probed.
518  */
519 static const struct lpss_device_links lpss_device_links[] = {
520 	/* CHT External sdcard slot controller depends on PMIC I2C ctrl */
521 	{"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
522 	/* CHT iGPU depends on PMIC I2C controller */
523 	{"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
524 	/* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
525 	{"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
526 	 i2c1_dep_missing_dmi_ids},
527 	/* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
528 	{"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
529 	/* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
530 	{"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
531 };
532 
533 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
534 				  const struct lpss_device_links *link)
535 {
536 	return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
537 }
538 
539 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
540 				  const struct lpss_device_links *link)
541 {
542 	return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
543 }
544 
545 struct hid_uid {
546 	const char *hid;
547 	const char *uid;
548 };
549 
550 static int match_hid_uid(struct device *dev, const void *data)
551 {
552 	struct acpi_device *adev = ACPI_COMPANION(dev);
553 	const struct hid_uid *id = data;
554 
555 	if (!adev)
556 		return 0;
557 
558 	return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
559 }
560 
561 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
562 {
563 	struct device *dev;
564 
565 	struct hid_uid data = {
566 		.hid = hid,
567 		.uid = uid,
568 	};
569 
570 	dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
571 	if (dev)
572 		return dev;
573 
574 	return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
575 }
576 
577 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
578 {
579 	struct acpi_handle_list dep_devices;
580 	acpi_status status;
581 	int i;
582 
583 	if (!acpi_has_method(adev->handle, "_DEP"))
584 		return false;
585 
586 	status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
587 					 &dep_devices);
588 	if (ACPI_FAILURE(status)) {
589 		dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
590 		return false;
591 	}
592 
593 	for (i = 0; i < dep_devices.count; i++) {
594 		if (dep_devices.handles[i] == handle)
595 			return true;
596 	}
597 
598 	return false;
599 }
600 
601 static void acpi_lpss_link_consumer(struct device *dev1,
602 				    const struct lpss_device_links *link)
603 {
604 	struct device *dev2;
605 
606 	dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
607 	if (!dev2)
608 		return;
609 
610 	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
611 	    || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
612 		device_link_add(dev2, dev1, link->flags);
613 
614 	put_device(dev2);
615 }
616 
617 static void acpi_lpss_link_supplier(struct device *dev1,
618 				    const struct lpss_device_links *link)
619 {
620 	struct device *dev2;
621 
622 	dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
623 	if (!dev2)
624 		return;
625 
626 	if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
627 	    || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
628 		device_link_add(dev1, dev2, link->flags);
629 
630 	put_device(dev2);
631 }
632 
633 static void acpi_lpss_create_device_links(struct acpi_device *adev,
634 					  struct platform_device *pdev)
635 {
636 	int i;
637 
638 	for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
639 		const struct lpss_device_links *link = &lpss_device_links[i];
640 
641 		if (acpi_lpss_is_supplier(adev, link))
642 			acpi_lpss_link_consumer(&pdev->dev, link);
643 
644 		if (acpi_lpss_is_consumer(adev, link))
645 			acpi_lpss_link_supplier(&pdev->dev, link);
646 	}
647 }
648 
649 static int acpi_lpss_create_device(struct acpi_device *adev,
650 				   const struct acpi_device_id *id)
651 {
652 	const struct lpss_device_desc *dev_desc;
653 	struct lpss_private_data *pdata;
654 	struct resource_entry *rentry;
655 	struct list_head resource_list;
656 	struct platform_device *pdev;
657 	int ret;
658 
659 	dev_desc = (const struct lpss_device_desc *)id->driver_data;
660 	if (!dev_desc) {
661 		pdev = acpi_create_platform_device(adev, NULL);
662 		return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
663 	}
664 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
665 	if (!pdata)
666 		return -ENOMEM;
667 
668 	INIT_LIST_HEAD(&resource_list);
669 	ret = acpi_dev_get_memory_resources(adev, &resource_list);
670 	if (ret < 0)
671 		goto err_out;
672 
673 	rentry = list_first_entry_or_null(&resource_list, struct resource_entry, node);
674 	if (rentry) {
675 		if (dev_desc->prv_size_override)
676 			pdata->mmio_size = dev_desc->prv_size_override;
677 		else
678 			pdata->mmio_size = resource_size(rentry->res);
679 		pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);
680 	}
681 
682 	acpi_dev_free_resource_list(&resource_list);
683 
684 	if (!pdata->mmio_base) {
685 		/* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
686 		adev->pnp.type.platform_id = 0;
687 		goto out_free;
688 	}
689 
690 	pdata->adev = adev;
691 	pdata->dev_desc = dev_desc;
692 
693 	if (dev_desc->setup)
694 		dev_desc->setup(pdata);
695 
696 	if (dev_desc->flags & LPSS_CLK) {
697 		ret = register_device_clock(adev, pdata);
698 		if (ret)
699 			goto out_free;
700 	}
701 
702 	/*
703 	 * This works around a known issue in ACPI tables where LPSS devices
704 	 * have _PS0 and _PS3 without _PSC (and no power resources), so
705 	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
706 	 */
707 	acpi_device_fix_up_power(adev);
708 
709 	adev->driver_data = pdata;
710 	pdev = acpi_create_platform_device(adev, dev_desc->properties);
711 	if (IS_ERR_OR_NULL(pdev)) {
712 		adev->driver_data = NULL;
713 		ret = PTR_ERR(pdev);
714 		goto err_out;
715 	}
716 
717 	acpi_lpss_create_device_links(adev, pdev);
718 	return 1;
719 
720 out_free:
721 	/* Skip the device, but continue the namespace scan */
722 	ret = 0;
723 err_out:
724 	kfree(pdata);
725 	return ret;
726 }
727 
728 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
729 {
730 	return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
731 }
732 
733 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
734 			     unsigned int reg)
735 {
736 	writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
737 }
738 
739 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
740 {
741 	struct acpi_device *adev = ACPI_COMPANION(dev);
742 	struct lpss_private_data *pdata;
743 	unsigned long flags;
744 	int ret;
745 
746 	if (WARN_ON(!adev))
747 		return -ENODEV;
748 
749 	spin_lock_irqsave(&dev->power.lock, flags);
750 	if (pm_runtime_suspended(dev)) {
751 		ret = -EAGAIN;
752 		goto out;
753 	}
754 	pdata = acpi_driver_data(adev);
755 	if (WARN_ON(!pdata || !pdata->mmio_base)) {
756 		ret = -ENODEV;
757 		goto out;
758 	}
759 	*val = __lpss_reg_read(pdata, reg);
760 	ret = 0;
761 
762  out:
763 	spin_unlock_irqrestore(&dev->power.lock, flags);
764 	return ret;
765 }
766 
767 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
768 			     char *buf)
769 {
770 	u32 ltr_value = 0;
771 	unsigned int reg;
772 	int ret;
773 
774 	reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
775 	ret = lpss_reg_read(dev, reg, &ltr_value);
776 	if (ret)
777 		return ret;
778 
779 	return sysfs_emit(buf, "%08x\n", ltr_value);
780 }
781 
782 static ssize_t lpss_ltr_mode_show(struct device *dev,
783 				  struct device_attribute *attr, char *buf)
784 {
785 	u32 ltr_mode = 0;
786 	char *outstr;
787 	int ret;
788 
789 	ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
790 	if (ret)
791 		return ret;
792 
793 	outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
794 	return sprintf(buf, "%s\n", outstr);
795 }
796 
797 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
798 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
799 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
800 
801 static struct attribute *lpss_attrs[] = {
802 	&dev_attr_auto_ltr.attr,
803 	&dev_attr_sw_ltr.attr,
804 	&dev_attr_ltr_mode.attr,
805 	NULL,
806 };
807 
808 static const struct attribute_group lpss_attr_group = {
809 	.attrs = lpss_attrs,
810 	.name = "lpss_ltr",
811 };
812 
813 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
814 {
815 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
816 	u32 ltr_mode, ltr_val;
817 
818 	ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
819 	if (val < 0) {
820 		if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
821 			ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
822 			__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
823 		}
824 		return;
825 	}
826 	ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
827 	if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
828 		ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
829 		val = LPSS_LTR_MAX_VAL;
830 	} else if (val > LPSS_LTR_MAX_VAL) {
831 		ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
832 		val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
833 	} else {
834 		ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
835 	}
836 	ltr_val |= val;
837 	__lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
838 	if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
839 		ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
840 		__lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
841 	}
842 }
843 
844 #ifdef CONFIG_PM
845 /**
846  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
847  * @dev: LPSS device
848  * @pdata: pointer to the private data of the LPSS device
849  *
850  * Most LPSS devices have private registers which may loose their context when
851  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
852  * prv_reg_ctx array.
853  */
854 static void acpi_lpss_save_ctx(struct device *dev,
855 			       struct lpss_private_data *pdata)
856 {
857 	unsigned int i;
858 
859 	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
860 		unsigned long offset = i * sizeof(u32);
861 
862 		pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
863 		dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
864 			pdata->prv_reg_ctx[i], offset);
865 	}
866 }
867 
868 /**
869  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
870  * @dev: LPSS device
871  * @pdata: pointer to the private data of the LPSS device
872  *
873  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
874  */
875 static void acpi_lpss_restore_ctx(struct device *dev,
876 				  struct lpss_private_data *pdata)
877 {
878 	unsigned int i;
879 
880 	for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
881 		unsigned long offset = i * sizeof(u32);
882 
883 		__lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
884 		dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
885 			pdata->prv_reg_ctx[i], offset);
886 	}
887 }
888 
889 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
890 {
891 	/*
892 	 * The following delay is needed or the subsequent write operations may
893 	 * fail. The LPSS devices are actually PCI devices and the PCI spec
894 	 * expects 10ms delay before the device can be accessed after D3 to D0
895 	 * transition. However some platforms like BSW does not need this delay.
896 	 */
897 	unsigned int delay = 10;	/* default 10ms delay */
898 
899 	if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
900 		delay = 0;
901 
902 	msleep(delay);
903 }
904 
905 static int acpi_lpss_activate(struct device *dev)
906 {
907 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
908 	int ret;
909 
910 	ret = acpi_dev_resume(dev);
911 	if (ret)
912 		return ret;
913 
914 	acpi_lpss_d3_to_d0_delay(pdata);
915 
916 	/*
917 	 * This is called only on ->probe() stage where a device is either in
918 	 * known state defined by BIOS or most likely powered off. Due to this
919 	 * we have to deassert reset line to be sure that ->probe() will
920 	 * recognize the device.
921 	 */
922 	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
923 		lpss_deassert_reset(pdata);
924 
925 #ifdef CONFIG_PM
926 	if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
927 		acpi_lpss_save_ctx(dev, pdata);
928 #endif
929 
930 	return 0;
931 }
932 
933 static void acpi_lpss_dismiss(struct device *dev)
934 {
935 	acpi_dev_suspend(dev, false);
936 }
937 
938 /* IOSF SB for LPSS island */
939 #define LPSS_IOSF_UNIT_LPIOEP		0xA0
940 #define LPSS_IOSF_UNIT_LPIO1		0xAB
941 #define LPSS_IOSF_UNIT_LPIO2		0xAC
942 
943 #define LPSS_IOSF_PMCSR			0x84
944 #define LPSS_PMCSR_D0			0
945 #define LPSS_PMCSR_D3hot		3
946 #define LPSS_PMCSR_Dx_MASK		GENMASK(1, 0)
947 
948 #define LPSS_IOSF_GPIODEF0		0x154
949 #define LPSS_GPIODEF0_DMA1_D3		BIT(2)
950 #define LPSS_GPIODEF0_DMA2_D3		BIT(3)
951 #define LPSS_GPIODEF0_DMA_D3_MASK	GENMASK(3, 2)
952 #define LPSS_GPIODEF0_DMA_LLP		BIT(13)
953 
954 static DEFINE_MUTEX(lpss_iosf_mutex);
955 static bool lpss_iosf_d3_entered = true;
956 
957 static void lpss_iosf_enter_d3_state(void)
958 {
959 	u32 value1 = 0;
960 	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
961 	u32 value2 = LPSS_PMCSR_D3hot;
962 	u32 mask2 = LPSS_PMCSR_Dx_MASK;
963 	/*
964 	 * PMC provides an information about actual status of the LPSS devices.
965 	 * Here we read the values related to LPSS power island, i.e. LPSS
966 	 * devices, excluding both LPSS DMA controllers, along with SCC domain.
967 	 */
968 	u32 func_dis, d3_sts_0, pmc_status;
969 	int ret;
970 
971 	ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
972 	if (ret)
973 		return;
974 
975 	mutex_lock(&lpss_iosf_mutex);
976 
977 	ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
978 	if (ret)
979 		goto exit;
980 
981 	/*
982 	 * Get the status of entire LPSS power island per device basis.
983 	 * Shutdown both LPSS DMA controllers if and only if all other devices
984 	 * are already in D3hot.
985 	 */
986 	pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
987 	if (pmc_status)
988 		goto exit;
989 
990 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
991 			LPSS_IOSF_PMCSR, value2, mask2);
992 
993 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
994 			LPSS_IOSF_PMCSR, value2, mask2);
995 
996 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
997 			LPSS_IOSF_GPIODEF0, value1, mask1);
998 
999 	lpss_iosf_d3_entered = true;
1000 
1001 exit:
1002 	mutex_unlock(&lpss_iosf_mutex);
1003 }
1004 
1005 static void lpss_iosf_exit_d3_state(void)
1006 {
1007 	u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
1008 		     LPSS_GPIODEF0_DMA_LLP;
1009 	u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
1010 	u32 value2 = LPSS_PMCSR_D0;
1011 	u32 mask2 = LPSS_PMCSR_Dx_MASK;
1012 
1013 	mutex_lock(&lpss_iosf_mutex);
1014 
1015 	if (!lpss_iosf_d3_entered)
1016 		goto exit;
1017 
1018 	lpss_iosf_d3_entered = false;
1019 
1020 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
1021 			LPSS_IOSF_GPIODEF0, value1, mask1);
1022 
1023 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1024 			LPSS_IOSF_PMCSR, value2, mask2);
1025 
1026 	iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1027 			LPSS_IOSF_PMCSR, value2, mask2);
1028 
1029 exit:
1030 	mutex_unlock(&lpss_iosf_mutex);
1031 }
1032 
1033 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1034 {
1035 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1036 	int ret;
1037 
1038 	if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1039 		acpi_lpss_save_ctx(dev, pdata);
1040 
1041 	ret = acpi_dev_suspend(dev, wakeup);
1042 
1043 	/*
1044 	 * This call must be last in the sequence, otherwise PMC will return
1045 	 * wrong status for devices being about to be powered off. See
1046 	 * lpss_iosf_enter_d3_state() for further information.
1047 	 */
1048 	if (acpi_target_system_state() == ACPI_STATE_S0 &&
1049 	    lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1050 		lpss_iosf_enter_d3_state();
1051 
1052 	return ret;
1053 }
1054 
1055 static int acpi_lpss_resume(struct device *dev)
1056 {
1057 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1058 	int ret;
1059 
1060 	/*
1061 	 * This call is kept first to be in symmetry with
1062 	 * acpi_lpss_runtime_suspend() one.
1063 	 */
1064 	if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1065 		lpss_iosf_exit_d3_state();
1066 
1067 	ret = acpi_dev_resume(dev);
1068 	if (ret)
1069 		return ret;
1070 
1071 	acpi_lpss_d3_to_d0_delay(pdata);
1072 
1073 	if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1074 		acpi_lpss_restore_ctx(dev, pdata);
1075 
1076 	return 0;
1077 }
1078 
1079 #ifdef CONFIG_PM_SLEEP
1080 static int acpi_lpss_do_suspend_late(struct device *dev)
1081 {
1082 	int ret;
1083 
1084 	if (dev_pm_skip_suspend(dev))
1085 		return 0;
1086 
1087 	ret = pm_generic_suspend_late(dev);
1088 	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1089 }
1090 
1091 static int acpi_lpss_suspend_late(struct device *dev)
1092 {
1093 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1094 
1095 	if (pdata->dev_desc->resume_from_noirq)
1096 		return 0;
1097 
1098 	return acpi_lpss_do_suspend_late(dev);
1099 }
1100 
1101 static int acpi_lpss_suspend_noirq(struct device *dev)
1102 {
1103 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1104 	int ret;
1105 
1106 	if (pdata->dev_desc->resume_from_noirq) {
1107 		/*
1108 		 * The driver's ->suspend_late callback will be invoked by
1109 		 * acpi_lpss_do_suspend_late(), with the assumption that the
1110 		 * driver really wanted to run that code in ->suspend_noirq, but
1111 		 * it could not run after acpi_dev_suspend() and the driver
1112 		 * expected the latter to be called in the "late" phase.
1113 		 */
1114 		ret = acpi_lpss_do_suspend_late(dev);
1115 		if (ret)
1116 			return ret;
1117 	}
1118 
1119 	return acpi_subsys_suspend_noirq(dev);
1120 }
1121 
1122 static int acpi_lpss_do_resume_early(struct device *dev)
1123 {
1124 	int ret = acpi_lpss_resume(dev);
1125 
1126 	return ret ? ret : pm_generic_resume_early(dev);
1127 }
1128 
1129 static int acpi_lpss_resume_early(struct device *dev)
1130 {
1131 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1132 
1133 	if (pdata->dev_desc->resume_from_noirq)
1134 		return 0;
1135 
1136 	if (dev_pm_skip_resume(dev))
1137 		return 0;
1138 
1139 	return acpi_lpss_do_resume_early(dev);
1140 }
1141 
1142 static int acpi_lpss_resume_noirq(struct device *dev)
1143 {
1144 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1145 	int ret;
1146 
1147 	/* Follow acpi_subsys_resume_noirq(). */
1148 	if (dev_pm_skip_resume(dev))
1149 		return 0;
1150 
1151 	ret = pm_generic_resume_noirq(dev);
1152 	if (ret)
1153 		return ret;
1154 
1155 	if (!pdata->dev_desc->resume_from_noirq)
1156 		return 0;
1157 
1158 	/*
1159 	 * The driver's ->resume_early callback will be invoked by
1160 	 * acpi_lpss_do_resume_early(), with the assumption that the driver
1161 	 * really wanted to run that code in ->resume_noirq, but it could not
1162 	 * run before acpi_dev_resume() and the driver expected the latter to be
1163 	 * called in the "early" phase.
1164 	 */
1165 	return acpi_lpss_do_resume_early(dev);
1166 }
1167 
1168 static int acpi_lpss_do_restore_early(struct device *dev)
1169 {
1170 	int ret = acpi_lpss_resume(dev);
1171 
1172 	return ret ? ret : pm_generic_restore_early(dev);
1173 }
1174 
1175 static int acpi_lpss_restore_early(struct device *dev)
1176 {
1177 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1178 
1179 	if (pdata->dev_desc->resume_from_noirq)
1180 		return 0;
1181 
1182 	return acpi_lpss_do_restore_early(dev);
1183 }
1184 
1185 static int acpi_lpss_restore_noirq(struct device *dev)
1186 {
1187 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1188 	int ret;
1189 
1190 	ret = pm_generic_restore_noirq(dev);
1191 	if (ret)
1192 		return ret;
1193 
1194 	if (!pdata->dev_desc->resume_from_noirq)
1195 		return 0;
1196 
1197 	/* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1198 	return acpi_lpss_do_restore_early(dev);
1199 }
1200 
1201 static int acpi_lpss_do_poweroff_late(struct device *dev)
1202 {
1203 	int ret = pm_generic_poweroff_late(dev);
1204 
1205 	return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1206 }
1207 
1208 static int acpi_lpss_poweroff_late(struct device *dev)
1209 {
1210 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1211 
1212 	if (dev_pm_skip_suspend(dev))
1213 		return 0;
1214 
1215 	if (pdata->dev_desc->resume_from_noirq)
1216 		return 0;
1217 
1218 	return acpi_lpss_do_poweroff_late(dev);
1219 }
1220 
1221 static int acpi_lpss_poweroff_noirq(struct device *dev)
1222 {
1223 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1224 
1225 	if (dev_pm_skip_suspend(dev))
1226 		return 0;
1227 
1228 	if (pdata->dev_desc->resume_from_noirq) {
1229 		/* This is analogous to the acpi_lpss_suspend_noirq() case. */
1230 		int ret = acpi_lpss_do_poweroff_late(dev);
1231 
1232 		if (ret)
1233 			return ret;
1234 	}
1235 
1236 	return pm_generic_poweroff_noirq(dev);
1237 }
1238 #endif /* CONFIG_PM_SLEEP */
1239 
1240 static int acpi_lpss_runtime_suspend(struct device *dev)
1241 {
1242 	int ret = pm_generic_runtime_suspend(dev);
1243 
1244 	return ret ? ret : acpi_lpss_suspend(dev, true);
1245 }
1246 
1247 static int acpi_lpss_runtime_resume(struct device *dev)
1248 {
1249 	int ret = acpi_lpss_resume(dev);
1250 
1251 	return ret ? ret : pm_generic_runtime_resume(dev);
1252 }
1253 #endif /* CONFIG_PM */
1254 
1255 static struct dev_pm_domain acpi_lpss_pm_domain = {
1256 #ifdef CONFIG_PM
1257 	.activate = acpi_lpss_activate,
1258 	.dismiss = acpi_lpss_dismiss,
1259 #endif
1260 	.ops = {
1261 #ifdef CONFIG_PM
1262 #ifdef CONFIG_PM_SLEEP
1263 		.prepare = acpi_subsys_prepare,
1264 		.complete = acpi_subsys_complete,
1265 		.suspend = acpi_subsys_suspend,
1266 		.suspend_late = acpi_lpss_suspend_late,
1267 		.suspend_noirq = acpi_lpss_suspend_noirq,
1268 		.resume_noirq = acpi_lpss_resume_noirq,
1269 		.resume_early = acpi_lpss_resume_early,
1270 		.freeze = acpi_subsys_freeze,
1271 		.poweroff = acpi_subsys_poweroff,
1272 		.poweroff_late = acpi_lpss_poweroff_late,
1273 		.poweroff_noirq = acpi_lpss_poweroff_noirq,
1274 		.restore_noirq = acpi_lpss_restore_noirq,
1275 		.restore_early = acpi_lpss_restore_early,
1276 #endif
1277 		.runtime_suspend = acpi_lpss_runtime_suspend,
1278 		.runtime_resume = acpi_lpss_runtime_resume,
1279 #endif
1280 	},
1281 };
1282 
1283 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1284 				     unsigned long action, void *data)
1285 {
1286 	struct platform_device *pdev = to_platform_device(data);
1287 	struct lpss_private_data *pdata;
1288 	struct acpi_device *adev;
1289 	const struct acpi_device_id *id;
1290 
1291 	id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1292 	if (!id || !id->driver_data)
1293 		return 0;
1294 
1295 	adev = ACPI_COMPANION(&pdev->dev);
1296 	if (!adev)
1297 		return 0;
1298 
1299 	pdata = acpi_driver_data(adev);
1300 	if (!pdata)
1301 		return 0;
1302 
1303 	if (pdata->mmio_base &&
1304 	    pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1305 		dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1306 		return 0;
1307 	}
1308 
1309 	switch (action) {
1310 	case BUS_NOTIFY_BIND_DRIVER:
1311 		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1312 		break;
1313 	case BUS_NOTIFY_DRIVER_NOT_BOUND:
1314 	case BUS_NOTIFY_UNBOUND_DRIVER:
1315 		dev_pm_domain_set(&pdev->dev, NULL);
1316 		break;
1317 	case BUS_NOTIFY_ADD_DEVICE:
1318 		dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1319 		if (pdata->dev_desc->flags & LPSS_LTR)
1320 			return sysfs_create_group(&pdev->dev.kobj,
1321 						  &lpss_attr_group);
1322 		break;
1323 	case BUS_NOTIFY_DEL_DEVICE:
1324 		if (pdata->dev_desc->flags & LPSS_LTR)
1325 			sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1326 		dev_pm_domain_set(&pdev->dev, NULL);
1327 		break;
1328 	default:
1329 		break;
1330 	}
1331 
1332 	return 0;
1333 }
1334 
1335 static struct notifier_block acpi_lpss_nb = {
1336 	.notifier_call = acpi_lpss_platform_notify,
1337 };
1338 
1339 static void acpi_lpss_bind(struct device *dev)
1340 {
1341 	struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1342 
1343 	if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1344 		return;
1345 
1346 	if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1347 		dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1348 	else
1349 		dev_err(dev, "MMIO size insufficient to access LTR\n");
1350 }
1351 
1352 static void acpi_lpss_unbind(struct device *dev)
1353 {
1354 	dev->power.set_latency_tolerance = NULL;
1355 }
1356 
1357 static struct acpi_scan_handler lpss_handler = {
1358 	.ids = acpi_lpss_device_ids,
1359 	.attach = acpi_lpss_create_device,
1360 	.bind = acpi_lpss_bind,
1361 	.unbind = acpi_lpss_unbind,
1362 };
1363 
1364 void __init acpi_lpss_init(void)
1365 {
1366 	const struct x86_cpu_id *id;
1367 	int ret;
1368 
1369 	ret = lpss_atom_clk_init();
1370 	if (ret)
1371 		return;
1372 
1373 	id = x86_match_cpu(lpss_cpu_ids);
1374 	if (id)
1375 		lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1376 
1377 	bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1378 	acpi_scan_add_handler(&lpss_handler);
1379 }
1380 
1381 #else
1382 
1383 static struct acpi_scan_handler lpss_handler = {
1384 	.ids = acpi_lpss_device_ids,
1385 };
1386 
1387 void __init acpi_lpss_init(void)
1388 {
1389 	acpi_scan_add_handler(&lpss_handler);
1390 }
1391 
1392 #endif /* CONFIG_X86_INTEL_LPSS */
1393