1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/mutex.h> 16 #include <linux/pci.h> 17 #include <linux/platform_device.h> 18 #include <linux/platform_data/x86/clk-lpss.h> 19 #include <linux/platform_data/x86/pmc_atom.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pwm.h> 23 #include <linux/suspend.h> 24 #include <linux/delay.h> 25 26 #include "internal.h" 27 28 ACPI_MODULE_NAME("acpi_lpss"); 29 30 #ifdef CONFIG_X86_INTEL_LPSS 31 32 #include <asm/cpu_device_id.h> 33 #include <asm/intel-family.h> 34 #include <asm/iosf_mbi.h> 35 36 #define LPSS_ADDR(desc) ((unsigned long)&desc) 37 38 #define LPSS_CLK_SIZE 0x04 39 #define LPSS_LTR_SIZE 0x18 40 41 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 43 #define LPSS_RESETS 0x04 44 #define LPSS_RESETS_RESET_FUNC BIT(0) 45 #define LPSS_RESETS_RESET_APB BIT(1) 46 #define LPSS_GENERAL 0x08 47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 49 #define LPSS_SW_LTR 0x10 50 #define LPSS_AUTO_LTR 0x14 51 #define LPSS_LTR_SNOOP_REQ BIT(15) 52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 53 #define LPSS_LTR_SNOOP_LAT_1US 0x800 54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 57 #define LPSS_LTR_MAX_VAL 0x3FF 58 #define LPSS_TX_INT 0x20 59 #define LPSS_TX_INT_MASK BIT(1) 60 61 #define LPSS_PRV_REG_COUNT 9 62 63 /* LPSS Flags */ 64 #define LPSS_CLK BIT(0) 65 #define LPSS_CLK_GATE BIT(1) 66 #define LPSS_CLK_DIVIDER BIT(2) 67 #define LPSS_LTR BIT(3) 68 #define LPSS_SAVE_CTX BIT(4) 69 #define LPSS_NO_D3_DELAY BIT(5) 70 71 /* Crystal Cove PMIC shares same ACPI ID between different platforms */ 72 #define BYT_CRC_HRV 2 73 #define CHT_CRC_HRV 3 74 75 struct lpss_private_data; 76 77 struct lpss_device_desc { 78 unsigned int flags; 79 const char *clk_con_id; 80 unsigned int prv_offset; 81 size_t prv_size_override; 82 struct property_entry *properties; 83 void (*setup)(struct lpss_private_data *pdata); 84 bool resume_from_noirq; 85 }; 86 87 static const struct lpss_device_desc lpss_dma_desc = { 88 .flags = LPSS_CLK, 89 }; 90 91 struct lpss_private_data { 92 struct acpi_device *adev; 93 void __iomem *mmio_base; 94 resource_size_t mmio_size; 95 unsigned int fixed_clk_rate; 96 struct clk *clk; 97 const struct lpss_device_desc *dev_desc; 98 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 99 }; 100 101 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 102 static u32 pmc_atom_d3_mask = 0xfe000ffe; 103 104 /* LPSS run time quirks */ 105 static unsigned int lpss_quirks; 106 107 /* 108 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 109 * 110 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 111 * it can be powered off automatically whenever the last LPSS device goes down. 112 * In case of no power any access to the DMA controller will hang the system. 113 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 114 * well as on ASuS T100TA transformer. 115 * 116 * This quirk overrides power state of entire LPSS island to keep DMA powered 117 * on whenever we have at least one other device in use. 118 */ 119 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 120 121 /* UART Component Parameter Register */ 122 #define LPSS_UART_CPR 0xF4 123 #define LPSS_UART_CPR_AFCE BIT(4) 124 125 static void lpss_uart_setup(struct lpss_private_data *pdata) 126 { 127 unsigned int offset; 128 u32 val; 129 130 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 131 val = readl(pdata->mmio_base + offset); 132 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 133 134 val = readl(pdata->mmio_base + LPSS_UART_CPR); 135 if (!(val & LPSS_UART_CPR_AFCE)) { 136 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 137 val = readl(pdata->mmio_base + offset); 138 val |= LPSS_GENERAL_UART_RTS_OVRD; 139 writel(val, pdata->mmio_base + offset); 140 } 141 } 142 143 static void lpss_deassert_reset(struct lpss_private_data *pdata) 144 { 145 unsigned int offset; 146 u32 val; 147 148 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 149 val = readl(pdata->mmio_base + offset); 150 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 151 writel(val, pdata->mmio_base + offset); 152 } 153 154 /* 155 * BYT PWM used for backlight control by the i915 driver on systems without 156 * the Crystal Cove PMIC. 157 */ 158 static struct pwm_lookup byt_pwm_lookup[] = { 159 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 160 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 161 "pwm-lpss-platform"), 162 }; 163 164 static void byt_pwm_setup(struct lpss_private_data *pdata) 165 { 166 struct acpi_device *adev = pdata->adev; 167 168 /* Only call pwm_add_table for the first PWM controller */ 169 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 170 return; 171 172 if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV)) 173 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 174 } 175 176 #define LPSS_I2C_ENABLE 0x6c 177 178 static void byt_i2c_setup(struct lpss_private_data *pdata) 179 { 180 const char *uid_str = acpi_device_uid(pdata->adev); 181 acpi_handle handle = pdata->adev->handle; 182 unsigned long long shared_host = 0; 183 acpi_status status; 184 long uid = 0; 185 186 /* Expected to always be true, but better safe then sorry */ 187 if (uid_str) 188 uid = simple_strtol(uid_str, NULL, 10); 189 190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 192 if (ACPI_SUCCESS(status) && shared_host && uid) 193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 194 195 lpss_deassert_reset(pdata); 196 197 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 198 pdata->fixed_clk_rate = 133000000; 199 200 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 201 } 202 203 /* BSW PWM used for backlight control by the i915 driver */ 204 static struct pwm_lookup bsw_pwm_lookup[] = { 205 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 206 "pwm_backlight", 0, PWM_POLARITY_NORMAL, 207 "pwm-lpss-platform"), 208 }; 209 210 static void bsw_pwm_setup(struct lpss_private_data *pdata) 211 { 212 struct acpi_device *adev = pdata->adev; 213 214 /* Only call pwm_add_table for the first PWM controller */ 215 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 216 return; 217 218 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 219 } 220 221 static const struct lpss_device_desc lpt_dev_desc = { 222 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 223 | LPSS_SAVE_CTX, 224 .prv_offset = 0x800, 225 }; 226 227 static const struct lpss_device_desc lpt_i2c_dev_desc = { 228 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 229 .prv_offset = 0x800, 230 }; 231 232 static struct property_entry uart_properties[] = { 233 PROPERTY_ENTRY_U32("reg-io-width", 4), 234 PROPERTY_ENTRY_U32("reg-shift", 2), 235 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 236 { }, 237 }; 238 239 static const struct lpss_device_desc lpt_uart_dev_desc = { 240 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 241 | LPSS_SAVE_CTX, 242 .clk_con_id = "baudclk", 243 .prv_offset = 0x800, 244 .setup = lpss_uart_setup, 245 .properties = uart_properties, 246 }; 247 248 static const struct lpss_device_desc lpt_sdio_dev_desc = { 249 .flags = LPSS_LTR, 250 .prv_offset = 0x1000, 251 .prv_size_override = 0x1018, 252 }; 253 254 static const struct lpss_device_desc byt_pwm_dev_desc = { 255 .flags = LPSS_SAVE_CTX, 256 .prv_offset = 0x800, 257 .setup = byt_pwm_setup, 258 }; 259 260 static const struct lpss_device_desc bsw_pwm_dev_desc = { 261 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 262 .prv_offset = 0x800, 263 .setup = bsw_pwm_setup, 264 }; 265 266 static const struct lpss_device_desc byt_uart_dev_desc = { 267 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 268 .clk_con_id = "baudclk", 269 .prv_offset = 0x800, 270 .setup = lpss_uart_setup, 271 .properties = uart_properties, 272 }; 273 274 static const struct lpss_device_desc bsw_uart_dev_desc = { 275 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 276 | LPSS_NO_D3_DELAY, 277 .clk_con_id = "baudclk", 278 .prv_offset = 0x800, 279 .setup = lpss_uart_setup, 280 .properties = uart_properties, 281 }; 282 283 static const struct lpss_device_desc byt_spi_dev_desc = { 284 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 285 .prv_offset = 0x400, 286 }; 287 288 static const struct lpss_device_desc byt_sdio_dev_desc = { 289 .flags = LPSS_CLK, 290 }; 291 292 static const struct lpss_device_desc byt_i2c_dev_desc = { 293 .flags = LPSS_CLK | LPSS_SAVE_CTX, 294 .prv_offset = 0x800, 295 .setup = byt_i2c_setup, 296 .resume_from_noirq = true, 297 }; 298 299 static const struct lpss_device_desc bsw_i2c_dev_desc = { 300 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 301 .prv_offset = 0x800, 302 .setup = byt_i2c_setup, 303 .resume_from_noirq = true, 304 }; 305 306 static const struct lpss_device_desc bsw_spi_dev_desc = { 307 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 308 | LPSS_NO_D3_DELAY, 309 .prv_offset = 0x400, 310 .setup = lpss_deassert_reset, 311 }; 312 313 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } 314 315 static const struct x86_cpu_id lpss_cpu_ids[] = { 316 ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ 317 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ 318 {} 319 }; 320 321 #else 322 323 #define LPSS_ADDR(desc) (0UL) 324 325 #endif /* CONFIG_X86_INTEL_LPSS */ 326 327 static const struct acpi_device_id acpi_lpss_device_ids[] = { 328 /* Generic LPSS devices */ 329 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 330 331 /* Lynxpoint LPSS devices */ 332 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 333 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 334 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 335 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 336 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 337 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 338 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 339 { "INT33C7", }, 340 341 /* BayTrail LPSS devices */ 342 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 343 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 344 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 345 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 346 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 347 { "INT33B2", }, 348 { "INT33FC", }, 349 350 /* Braswell LPSS devices */ 351 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 352 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 353 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 354 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 355 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 356 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 357 358 /* Broadwell LPSS devices */ 359 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 360 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 361 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 362 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 363 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 364 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 365 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 366 { "INT3437", }, 367 368 /* Wildcat Point LPSS devices */ 369 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 370 371 { } 372 }; 373 374 #ifdef CONFIG_X86_INTEL_LPSS 375 376 static int is_memory(struct acpi_resource *res, void *not_used) 377 { 378 struct resource r; 379 return !acpi_dev_resource_memory(res, &r); 380 } 381 382 /* LPSS main clock device. */ 383 static struct platform_device *lpss_clk_dev; 384 385 static inline void lpt_register_clock_device(void) 386 { 387 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 388 } 389 390 static int register_device_clock(struct acpi_device *adev, 391 struct lpss_private_data *pdata) 392 { 393 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 394 const char *devname = dev_name(&adev->dev); 395 struct clk *clk; 396 struct lpss_clk_data *clk_data; 397 const char *parent, *clk_name; 398 void __iomem *prv_base; 399 400 if (!lpss_clk_dev) 401 lpt_register_clock_device(); 402 403 clk_data = platform_get_drvdata(lpss_clk_dev); 404 if (!clk_data) 405 return -ENODEV; 406 clk = clk_data->clk; 407 408 if (!pdata->mmio_base 409 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 410 return -ENODATA; 411 412 parent = clk_data->name; 413 prv_base = pdata->mmio_base + dev_desc->prv_offset; 414 415 if (pdata->fixed_clk_rate) { 416 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 417 pdata->fixed_clk_rate); 418 goto out; 419 } 420 421 if (dev_desc->flags & LPSS_CLK_GATE) { 422 clk = clk_register_gate(NULL, devname, parent, 0, 423 prv_base, 0, 0, NULL); 424 parent = devname; 425 } 426 427 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 428 /* Prevent division by zero */ 429 if (!readl(prv_base)) 430 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 431 432 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 433 if (!clk_name) 434 return -ENOMEM; 435 clk = clk_register_fractional_divider(NULL, clk_name, parent, 436 0, prv_base, 437 1, 15, 16, 15, 0, NULL); 438 parent = clk_name; 439 440 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 441 if (!clk_name) { 442 kfree(parent); 443 return -ENOMEM; 444 } 445 clk = clk_register_gate(NULL, clk_name, parent, 446 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 447 prv_base, 31, 0, NULL); 448 kfree(parent); 449 kfree(clk_name); 450 } 451 out: 452 if (IS_ERR(clk)) 453 return PTR_ERR(clk); 454 455 pdata->clk = clk; 456 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 457 return 0; 458 } 459 460 struct lpss_device_links { 461 const char *supplier_hid; 462 const char *supplier_uid; 463 const char *consumer_hid; 464 const char *consumer_uid; 465 u32 flags; 466 }; 467 468 /* 469 * The _DEP method is used to identify dependencies but instead of creating 470 * device links for every handle in _DEP, only links in the following list are 471 * created. That is necessary because, in the general case, _DEP can refer to 472 * devices that might not have drivers, or that are on different buses, or where 473 * the supplier is not enumerated until after the consumer is probed. 474 */ 475 static const struct lpss_device_links lpss_device_links[] = { 476 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 477 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 478 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 479 }; 480 481 static bool hid_uid_match(struct acpi_device *adev, 482 const char *hid2, const char *uid2) 483 { 484 const char *hid1 = acpi_device_hid(adev); 485 const char *uid1 = acpi_device_uid(adev); 486 487 if (strcmp(hid1, hid2)) 488 return false; 489 490 if (!uid2) 491 return true; 492 493 return uid1 && !strcmp(uid1, uid2); 494 } 495 496 static bool acpi_lpss_is_supplier(struct acpi_device *adev, 497 const struct lpss_device_links *link) 498 { 499 return hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 500 } 501 502 static bool acpi_lpss_is_consumer(struct acpi_device *adev, 503 const struct lpss_device_links *link) 504 { 505 return hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 506 } 507 508 struct hid_uid { 509 const char *hid; 510 const char *uid; 511 }; 512 513 static int match_hid_uid(struct device *dev, const void *data) 514 { 515 struct acpi_device *adev = ACPI_COMPANION(dev); 516 const struct hid_uid *id = data; 517 518 if (!adev) 519 return 0; 520 521 return hid_uid_match(adev, id->hid, id->uid); 522 } 523 524 static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 525 { 526 struct device *dev; 527 528 struct hid_uid data = { 529 .hid = hid, 530 .uid = uid, 531 }; 532 533 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 534 if (dev) 535 return dev; 536 537 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 538 } 539 540 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 541 { 542 struct acpi_handle_list dep_devices; 543 acpi_status status; 544 int i; 545 546 if (!acpi_has_method(adev->handle, "_DEP")) 547 return false; 548 549 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 550 &dep_devices); 551 if (ACPI_FAILURE(status)) { 552 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 553 return false; 554 } 555 556 for (i = 0; i < dep_devices.count; i++) { 557 if (dep_devices.handles[i] == handle) 558 return true; 559 } 560 561 return false; 562 } 563 564 static void acpi_lpss_link_consumer(struct device *dev1, 565 const struct lpss_device_links *link) 566 { 567 struct device *dev2; 568 569 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 570 if (!dev2) 571 return; 572 573 if (acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 574 device_link_add(dev2, dev1, link->flags); 575 576 put_device(dev2); 577 } 578 579 static void acpi_lpss_link_supplier(struct device *dev1, 580 const struct lpss_device_links *link) 581 { 582 struct device *dev2; 583 584 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 585 if (!dev2) 586 return; 587 588 if (acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 589 device_link_add(dev1, dev2, link->flags); 590 591 put_device(dev2); 592 } 593 594 static void acpi_lpss_create_device_links(struct acpi_device *adev, 595 struct platform_device *pdev) 596 { 597 int i; 598 599 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 600 const struct lpss_device_links *link = &lpss_device_links[i]; 601 602 if (acpi_lpss_is_supplier(adev, link)) 603 acpi_lpss_link_consumer(&pdev->dev, link); 604 605 if (acpi_lpss_is_consumer(adev, link)) 606 acpi_lpss_link_supplier(&pdev->dev, link); 607 } 608 } 609 610 static int acpi_lpss_create_device(struct acpi_device *adev, 611 const struct acpi_device_id *id) 612 { 613 const struct lpss_device_desc *dev_desc; 614 struct lpss_private_data *pdata; 615 struct resource_entry *rentry; 616 struct list_head resource_list; 617 struct platform_device *pdev; 618 int ret; 619 620 dev_desc = (const struct lpss_device_desc *)id->driver_data; 621 if (!dev_desc) { 622 pdev = acpi_create_platform_device(adev, NULL); 623 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 624 } 625 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 626 if (!pdata) 627 return -ENOMEM; 628 629 INIT_LIST_HEAD(&resource_list); 630 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 631 if (ret < 0) 632 goto err_out; 633 634 list_for_each_entry(rentry, &resource_list, node) 635 if (resource_type(rentry->res) == IORESOURCE_MEM) { 636 if (dev_desc->prv_size_override) 637 pdata->mmio_size = dev_desc->prv_size_override; 638 else 639 pdata->mmio_size = resource_size(rentry->res); 640 pdata->mmio_base = ioremap(rentry->res->start, 641 pdata->mmio_size); 642 break; 643 } 644 645 acpi_dev_free_resource_list(&resource_list); 646 647 if (!pdata->mmio_base) { 648 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 649 adev->pnp.type.platform_id = 0; 650 /* Skip the device, but continue the namespace scan. */ 651 ret = 0; 652 goto err_out; 653 } 654 655 pdata->adev = adev; 656 pdata->dev_desc = dev_desc; 657 658 if (dev_desc->setup) 659 dev_desc->setup(pdata); 660 661 if (dev_desc->flags & LPSS_CLK) { 662 ret = register_device_clock(adev, pdata); 663 if (ret) { 664 /* Skip the device, but continue the namespace scan. */ 665 ret = 0; 666 goto err_out; 667 } 668 } 669 670 /* 671 * This works around a known issue in ACPI tables where LPSS devices 672 * have _PS0 and _PS3 without _PSC (and no power resources), so 673 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 674 */ 675 acpi_device_fix_up_power(adev); 676 677 adev->driver_data = pdata; 678 pdev = acpi_create_platform_device(adev, dev_desc->properties); 679 if (!IS_ERR_OR_NULL(pdev)) { 680 acpi_lpss_create_device_links(adev, pdev); 681 return 1; 682 } 683 684 ret = PTR_ERR(pdev); 685 adev->driver_data = NULL; 686 687 err_out: 688 kfree(pdata); 689 return ret; 690 } 691 692 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 693 { 694 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 695 } 696 697 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 698 unsigned int reg) 699 { 700 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 701 } 702 703 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 704 { 705 struct acpi_device *adev; 706 struct lpss_private_data *pdata; 707 unsigned long flags; 708 int ret; 709 710 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 711 if (WARN_ON(ret)) 712 return ret; 713 714 spin_lock_irqsave(&dev->power.lock, flags); 715 if (pm_runtime_suspended(dev)) { 716 ret = -EAGAIN; 717 goto out; 718 } 719 pdata = acpi_driver_data(adev); 720 if (WARN_ON(!pdata || !pdata->mmio_base)) { 721 ret = -ENODEV; 722 goto out; 723 } 724 *val = __lpss_reg_read(pdata, reg); 725 726 out: 727 spin_unlock_irqrestore(&dev->power.lock, flags); 728 return ret; 729 } 730 731 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 732 char *buf) 733 { 734 u32 ltr_value = 0; 735 unsigned int reg; 736 int ret; 737 738 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 739 ret = lpss_reg_read(dev, reg, <r_value); 740 if (ret) 741 return ret; 742 743 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 744 } 745 746 static ssize_t lpss_ltr_mode_show(struct device *dev, 747 struct device_attribute *attr, char *buf) 748 { 749 u32 ltr_mode = 0; 750 char *outstr; 751 int ret; 752 753 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 754 if (ret) 755 return ret; 756 757 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 758 return sprintf(buf, "%s\n", outstr); 759 } 760 761 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 762 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 763 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 764 765 static struct attribute *lpss_attrs[] = { 766 &dev_attr_auto_ltr.attr, 767 &dev_attr_sw_ltr.attr, 768 &dev_attr_ltr_mode.attr, 769 NULL, 770 }; 771 772 static const struct attribute_group lpss_attr_group = { 773 .attrs = lpss_attrs, 774 .name = "lpss_ltr", 775 }; 776 777 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 778 { 779 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 780 u32 ltr_mode, ltr_val; 781 782 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 783 if (val < 0) { 784 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 785 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 786 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 787 } 788 return; 789 } 790 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 791 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 792 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 793 val = LPSS_LTR_MAX_VAL; 794 } else if (val > LPSS_LTR_MAX_VAL) { 795 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 796 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 797 } else { 798 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 799 } 800 ltr_val |= val; 801 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 802 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 803 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 804 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 805 } 806 } 807 808 #ifdef CONFIG_PM 809 /** 810 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 811 * @dev: LPSS device 812 * @pdata: pointer to the private data of the LPSS device 813 * 814 * Most LPSS devices have private registers which may loose their context when 815 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 816 * prv_reg_ctx array. 817 */ 818 static void acpi_lpss_save_ctx(struct device *dev, 819 struct lpss_private_data *pdata) 820 { 821 unsigned int i; 822 823 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 824 unsigned long offset = i * sizeof(u32); 825 826 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 827 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 828 pdata->prv_reg_ctx[i], offset); 829 } 830 } 831 832 /** 833 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 834 * @dev: LPSS device 835 * @pdata: pointer to the private data of the LPSS device 836 * 837 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 838 */ 839 static void acpi_lpss_restore_ctx(struct device *dev, 840 struct lpss_private_data *pdata) 841 { 842 unsigned int i; 843 844 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 845 unsigned long offset = i * sizeof(u32); 846 847 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 848 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 849 pdata->prv_reg_ctx[i], offset); 850 } 851 } 852 853 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 854 { 855 /* 856 * The following delay is needed or the subsequent write operations may 857 * fail. The LPSS devices are actually PCI devices and the PCI spec 858 * expects 10ms delay before the device can be accessed after D3 to D0 859 * transition. However some platforms like BSW does not need this delay. 860 */ 861 unsigned int delay = 10; /* default 10ms delay */ 862 863 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 864 delay = 0; 865 866 msleep(delay); 867 } 868 869 static int acpi_lpss_activate(struct device *dev) 870 { 871 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 872 int ret; 873 874 ret = acpi_dev_resume(dev); 875 if (ret) 876 return ret; 877 878 acpi_lpss_d3_to_d0_delay(pdata); 879 880 /* 881 * This is called only on ->probe() stage where a device is either in 882 * known state defined by BIOS or most likely powered off. Due to this 883 * we have to deassert reset line to be sure that ->probe() will 884 * recognize the device. 885 */ 886 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 887 lpss_deassert_reset(pdata); 888 889 return 0; 890 } 891 892 static void acpi_lpss_dismiss(struct device *dev) 893 { 894 acpi_dev_suspend(dev, false); 895 } 896 897 /* IOSF SB for LPSS island */ 898 #define LPSS_IOSF_UNIT_LPIOEP 0xA0 899 #define LPSS_IOSF_UNIT_LPIO1 0xAB 900 #define LPSS_IOSF_UNIT_LPIO2 0xAC 901 902 #define LPSS_IOSF_PMCSR 0x84 903 #define LPSS_PMCSR_D0 0 904 #define LPSS_PMCSR_D3hot 3 905 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 906 907 #define LPSS_IOSF_GPIODEF0 0x154 908 #define LPSS_GPIODEF0_DMA1_D3 BIT(2) 909 #define LPSS_GPIODEF0_DMA2_D3 BIT(3) 910 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 911 #define LPSS_GPIODEF0_DMA_LLP BIT(13) 912 913 static DEFINE_MUTEX(lpss_iosf_mutex); 914 static bool lpss_iosf_d3_entered = true; 915 916 static void lpss_iosf_enter_d3_state(void) 917 { 918 u32 value1 = 0; 919 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 920 u32 value2 = LPSS_PMCSR_D3hot; 921 u32 mask2 = LPSS_PMCSR_Dx_MASK; 922 /* 923 * PMC provides an information about actual status of the LPSS devices. 924 * Here we read the values related to LPSS power island, i.e. LPSS 925 * devices, excluding both LPSS DMA controllers, along with SCC domain. 926 */ 927 u32 func_dis, d3_sts_0, pmc_status; 928 int ret; 929 930 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 931 if (ret) 932 return; 933 934 mutex_lock(&lpss_iosf_mutex); 935 936 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 937 if (ret) 938 goto exit; 939 940 /* 941 * Get the status of entire LPSS power island per device basis. 942 * Shutdown both LPSS DMA controllers if and only if all other devices 943 * are already in D3hot. 944 */ 945 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 946 if (pmc_status) 947 goto exit; 948 949 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 950 LPSS_IOSF_PMCSR, value2, mask2); 951 952 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 953 LPSS_IOSF_PMCSR, value2, mask2); 954 955 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 956 LPSS_IOSF_GPIODEF0, value1, mask1); 957 958 lpss_iosf_d3_entered = true; 959 960 exit: 961 mutex_unlock(&lpss_iosf_mutex); 962 } 963 964 static void lpss_iosf_exit_d3_state(void) 965 { 966 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 967 LPSS_GPIODEF0_DMA_LLP; 968 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 969 u32 value2 = LPSS_PMCSR_D0; 970 u32 mask2 = LPSS_PMCSR_Dx_MASK; 971 972 mutex_lock(&lpss_iosf_mutex); 973 974 if (!lpss_iosf_d3_entered) 975 goto exit; 976 977 lpss_iosf_d3_entered = false; 978 979 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 980 LPSS_IOSF_GPIODEF0, value1, mask1); 981 982 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 983 LPSS_IOSF_PMCSR, value2, mask2); 984 985 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 986 LPSS_IOSF_PMCSR, value2, mask2); 987 988 exit: 989 mutex_unlock(&lpss_iosf_mutex); 990 } 991 992 static int acpi_lpss_suspend(struct device *dev, bool wakeup) 993 { 994 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 995 int ret; 996 997 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 998 acpi_lpss_save_ctx(dev, pdata); 999 1000 ret = acpi_dev_suspend(dev, wakeup); 1001 1002 /* 1003 * This call must be last in the sequence, otherwise PMC will return 1004 * wrong status for devices being about to be powered off. See 1005 * lpss_iosf_enter_d3_state() for further information. 1006 */ 1007 if (acpi_target_system_state() == ACPI_STATE_S0 && 1008 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1009 lpss_iosf_enter_d3_state(); 1010 1011 return ret; 1012 } 1013 1014 static int acpi_lpss_resume(struct device *dev) 1015 { 1016 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1017 int ret; 1018 1019 /* 1020 * This call is kept first to be in symmetry with 1021 * acpi_lpss_runtime_suspend() one. 1022 */ 1023 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1024 lpss_iosf_exit_d3_state(); 1025 1026 ret = acpi_dev_resume(dev); 1027 if (ret) 1028 return ret; 1029 1030 acpi_lpss_d3_to_d0_delay(pdata); 1031 1032 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1033 acpi_lpss_restore_ctx(dev, pdata); 1034 1035 return 0; 1036 } 1037 1038 #ifdef CONFIG_PM_SLEEP 1039 static int acpi_lpss_do_suspend_late(struct device *dev) 1040 { 1041 int ret; 1042 1043 if (dev_pm_smart_suspend_and_suspended(dev)) 1044 return 0; 1045 1046 ret = pm_generic_suspend_late(dev); 1047 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1048 } 1049 1050 static int acpi_lpss_suspend_late(struct device *dev) 1051 { 1052 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1053 1054 if (pdata->dev_desc->resume_from_noirq) 1055 return 0; 1056 1057 return acpi_lpss_do_suspend_late(dev); 1058 } 1059 1060 static int acpi_lpss_suspend_noirq(struct device *dev) 1061 { 1062 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1063 int ret; 1064 1065 if (pdata->dev_desc->resume_from_noirq) { 1066 /* 1067 * The driver's ->suspend_late callback will be invoked by 1068 * acpi_lpss_do_suspend_late(), with the assumption that the 1069 * driver really wanted to run that code in ->suspend_noirq, but 1070 * it could not run after acpi_dev_suspend() and the driver 1071 * expected the latter to be called in the "late" phase. 1072 */ 1073 ret = acpi_lpss_do_suspend_late(dev); 1074 if (ret) 1075 return ret; 1076 } 1077 1078 return acpi_subsys_suspend_noirq(dev); 1079 } 1080 1081 static int acpi_lpss_do_resume_early(struct device *dev) 1082 { 1083 int ret = acpi_lpss_resume(dev); 1084 1085 return ret ? ret : pm_generic_resume_early(dev); 1086 } 1087 1088 static int acpi_lpss_resume_early(struct device *dev) 1089 { 1090 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1091 1092 if (pdata->dev_desc->resume_from_noirq) 1093 return 0; 1094 1095 return acpi_lpss_do_resume_early(dev); 1096 } 1097 1098 static int acpi_lpss_resume_noirq(struct device *dev) 1099 { 1100 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1101 int ret; 1102 1103 /* Follow acpi_subsys_resume_noirq(). */ 1104 if (dev_pm_may_skip_resume(dev)) 1105 return 0; 1106 1107 if (dev_pm_smart_suspend_and_suspended(dev)) 1108 pm_runtime_set_active(dev); 1109 1110 ret = pm_generic_resume_noirq(dev); 1111 if (ret) 1112 return ret; 1113 1114 if (!pdata->dev_desc->resume_from_noirq) 1115 return 0; 1116 1117 /* 1118 * The driver's ->resume_early callback will be invoked by 1119 * acpi_lpss_do_resume_early(), with the assumption that the driver 1120 * really wanted to run that code in ->resume_noirq, but it could not 1121 * run before acpi_dev_resume() and the driver expected the latter to be 1122 * called in the "early" phase. 1123 */ 1124 return acpi_lpss_do_resume_early(dev); 1125 } 1126 1127 static int acpi_lpss_do_restore_early(struct device *dev) 1128 { 1129 int ret = acpi_lpss_resume(dev); 1130 1131 return ret ? ret : pm_generic_restore_early(dev); 1132 } 1133 1134 static int acpi_lpss_restore_early(struct device *dev) 1135 { 1136 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1137 1138 if (pdata->dev_desc->resume_from_noirq) 1139 return 0; 1140 1141 return acpi_lpss_do_restore_early(dev); 1142 } 1143 1144 static int acpi_lpss_restore_noirq(struct device *dev) 1145 { 1146 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1147 int ret; 1148 1149 ret = pm_generic_restore_noirq(dev); 1150 if (ret) 1151 return ret; 1152 1153 if (!pdata->dev_desc->resume_from_noirq) 1154 return 0; 1155 1156 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1157 return acpi_lpss_do_restore_early(dev); 1158 } 1159 1160 static int acpi_lpss_do_poweroff_late(struct device *dev) 1161 { 1162 int ret = pm_generic_poweroff_late(dev); 1163 1164 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1165 } 1166 1167 static int acpi_lpss_poweroff_late(struct device *dev) 1168 { 1169 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1170 1171 if (dev_pm_smart_suspend_and_suspended(dev)) 1172 return 0; 1173 1174 if (pdata->dev_desc->resume_from_noirq) 1175 return 0; 1176 1177 return acpi_lpss_do_poweroff_late(dev); 1178 } 1179 1180 static int acpi_lpss_poweroff_noirq(struct device *dev) 1181 { 1182 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1183 1184 if (dev_pm_smart_suspend_and_suspended(dev)) 1185 return 0; 1186 1187 if (pdata->dev_desc->resume_from_noirq) { 1188 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1189 int ret = acpi_lpss_do_poweroff_late(dev); 1190 if (ret) 1191 return ret; 1192 } 1193 1194 return pm_generic_poweroff_noirq(dev); 1195 } 1196 #endif /* CONFIG_PM_SLEEP */ 1197 1198 static int acpi_lpss_runtime_suspend(struct device *dev) 1199 { 1200 int ret = pm_generic_runtime_suspend(dev); 1201 1202 return ret ? ret : acpi_lpss_suspend(dev, true); 1203 } 1204 1205 static int acpi_lpss_runtime_resume(struct device *dev) 1206 { 1207 int ret = acpi_lpss_resume(dev); 1208 1209 return ret ? ret : pm_generic_runtime_resume(dev); 1210 } 1211 #endif /* CONFIG_PM */ 1212 1213 static struct dev_pm_domain acpi_lpss_pm_domain = { 1214 #ifdef CONFIG_PM 1215 .activate = acpi_lpss_activate, 1216 .dismiss = acpi_lpss_dismiss, 1217 #endif 1218 .ops = { 1219 #ifdef CONFIG_PM 1220 #ifdef CONFIG_PM_SLEEP 1221 .prepare = acpi_subsys_prepare, 1222 .complete = acpi_subsys_complete, 1223 .suspend = acpi_subsys_suspend, 1224 .suspend_late = acpi_lpss_suspend_late, 1225 .suspend_noirq = acpi_lpss_suspend_noirq, 1226 .resume_noirq = acpi_lpss_resume_noirq, 1227 .resume_early = acpi_lpss_resume_early, 1228 .freeze = acpi_subsys_freeze, 1229 .poweroff = acpi_subsys_poweroff, 1230 .poweroff_late = acpi_lpss_poweroff_late, 1231 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1232 .restore_noirq = acpi_lpss_restore_noirq, 1233 .restore_early = acpi_lpss_restore_early, 1234 #endif 1235 .runtime_suspend = acpi_lpss_runtime_suspend, 1236 .runtime_resume = acpi_lpss_runtime_resume, 1237 #endif 1238 }, 1239 }; 1240 1241 static int acpi_lpss_platform_notify(struct notifier_block *nb, 1242 unsigned long action, void *data) 1243 { 1244 struct platform_device *pdev = to_platform_device(data); 1245 struct lpss_private_data *pdata; 1246 struct acpi_device *adev; 1247 const struct acpi_device_id *id; 1248 1249 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1250 if (!id || !id->driver_data) 1251 return 0; 1252 1253 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1254 return 0; 1255 1256 pdata = acpi_driver_data(adev); 1257 if (!pdata) 1258 return 0; 1259 1260 if (pdata->mmio_base && 1261 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1262 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1263 return 0; 1264 } 1265 1266 switch (action) { 1267 case BUS_NOTIFY_BIND_DRIVER: 1268 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1269 break; 1270 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1271 case BUS_NOTIFY_UNBOUND_DRIVER: 1272 dev_pm_domain_set(&pdev->dev, NULL); 1273 break; 1274 case BUS_NOTIFY_ADD_DEVICE: 1275 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1276 if (pdata->dev_desc->flags & LPSS_LTR) 1277 return sysfs_create_group(&pdev->dev.kobj, 1278 &lpss_attr_group); 1279 break; 1280 case BUS_NOTIFY_DEL_DEVICE: 1281 if (pdata->dev_desc->flags & LPSS_LTR) 1282 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1283 dev_pm_domain_set(&pdev->dev, NULL); 1284 break; 1285 default: 1286 break; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static struct notifier_block acpi_lpss_nb = { 1293 .notifier_call = acpi_lpss_platform_notify, 1294 }; 1295 1296 static void acpi_lpss_bind(struct device *dev) 1297 { 1298 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1299 1300 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1301 return; 1302 1303 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1304 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1305 else 1306 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1307 } 1308 1309 static void acpi_lpss_unbind(struct device *dev) 1310 { 1311 dev->power.set_latency_tolerance = NULL; 1312 } 1313 1314 static struct acpi_scan_handler lpss_handler = { 1315 .ids = acpi_lpss_device_ids, 1316 .attach = acpi_lpss_create_device, 1317 .bind = acpi_lpss_bind, 1318 .unbind = acpi_lpss_unbind, 1319 }; 1320 1321 void __init acpi_lpss_init(void) 1322 { 1323 const struct x86_cpu_id *id; 1324 int ret; 1325 1326 ret = lpt_clk_init(); 1327 if (ret) 1328 return; 1329 1330 id = x86_match_cpu(lpss_cpu_ids); 1331 if (id) 1332 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1333 1334 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1335 acpi_scan_add_handler(&lpss_handler); 1336 } 1337 1338 #else 1339 1340 static struct acpi_scan_handler lpss_handler = { 1341 .ids = acpi_lpss_device_ids, 1342 }; 1343 1344 void __init acpi_lpss_init(void) 1345 { 1346 acpi_scan_add_handler(&lpss_handler); 1347 } 1348 1349 #endif /* CONFIG_X86_INTEL_LPSS */ 1350