1 /* 2 * ACPI support for Intel Lynxpoint LPSS. 3 * 4 * Copyright (C) 2013, Intel Corporation 5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/clk-lpss.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/delay.h> 23 24 #include "internal.h" 25 26 ACPI_MODULE_NAME("acpi_lpss"); 27 28 #ifdef CONFIG_X86_INTEL_LPSS 29 30 #define LPSS_ADDR(desc) ((unsigned long)&desc) 31 32 #define LPSS_CLK_SIZE 0x04 33 #define LPSS_LTR_SIZE 0x18 34 35 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 37 #define LPSS_GENERAL 0x08 38 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 39 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 40 #define LPSS_SW_LTR 0x10 41 #define LPSS_AUTO_LTR 0x14 42 #define LPSS_LTR_SNOOP_REQ BIT(15) 43 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 44 #define LPSS_LTR_SNOOP_LAT_1US 0x800 45 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 46 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 47 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 48 #define LPSS_LTR_MAX_VAL 0x3FF 49 #define LPSS_TX_INT 0x20 50 #define LPSS_TX_INT_MASK BIT(1) 51 52 #define LPSS_PRV_REG_COUNT 9 53 54 struct lpss_shared_clock { 55 const char *name; 56 unsigned long rate; 57 struct clk *clk; 58 }; 59 60 struct lpss_private_data; 61 62 struct lpss_device_desc { 63 bool clk_required; 64 const char *clkdev_name; 65 bool ltr_required; 66 unsigned int prv_offset; 67 size_t prv_size_override; 68 bool clk_divider; 69 bool clk_gate; 70 bool save_ctx; 71 struct lpss_shared_clock *shared_clock; 72 void (*setup)(struct lpss_private_data *pdata); 73 }; 74 75 static struct lpss_device_desc lpss_dma_desc = { 76 .clk_required = true, 77 .clkdev_name = "hclk", 78 }; 79 80 struct lpss_private_data { 81 void __iomem *mmio_base; 82 resource_size_t mmio_size; 83 struct clk *clk; 84 const struct lpss_device_desc *dev_desc; 85 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 86 }; 87 88 static void lpss_uart_setup(struct lpss_private_data *pdata) 89 { 90 unsigned int offset; 91 u32 reg; 92 93 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 94 reg = readl(pdata->mmio_base + offset); 95 writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 96 97 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 98 reg = readl(pdata->mmio_base + offset); 99 writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset); 100 } 101 102 static struct lpss_device_desc lpt_dev_desc = { 103 .clk_required = true, 104 .prv_offset = 0x800, 105 .ltr_required = true, 106 .clk_divider = true, 107 .clk_gate = true, 108 }; 109 110 static struct lpss_device_desc lpt_i2c_dev_desc = { 111 .clk_required = true, 112 .prv_offset = 0x800, 113 .ltr_required = true, 114 .clk_gate = true, 115 }; 116 117 static struct lpss_device_desc lpt_uart_dev_desc = { 118 .clk_required = true, 119 .prv_offset = 0x800, 120 .ltr_required = true, 121 .clk_divider = true, 122 .clk_gate = true, 123 .setup = lpss_uart_setup, 124 }; 125 126 static struct lpss_device_desc lpt_sdio_dev_desc = { 127 .prv_offset = 0x1000, 128 .prv_size_override = 0x1018, 129 .ltr_required = true, 130 }; 131 132 static struct lpss_shared_clock pwm_clock = { 133 .name = "pwm_clk", 134 .rate = 25000000, 135 }; 136 137 static struct lpss_device_desc byt_pwm_dev_desc = { 138 .clk_required = true, 139 .save_ctx = true, 140 .shared_clock = &pwm_clock, 141 }; 142 143 static struct lpss_device_desc byt_uart_dev_desc = { 144 .clk_required = true, 145 .prv_offset = 0x800, 146 .clk_divider = true, 147 .clk_gate = true, 148 .save_ctx = true, 149 .setup = lpss_uart_setup, 150 }; 151 152 static struct lpss_device_desc byt_spi_dev_desc = { 153 .clk_required = true, 154 .prv_offset = 0x400, 155 .clk_divider = true, 156 .clk_gate = true, 157 .save_ctx = true, 158 }; 159 160 static struct lpss_device_desc byt_sdio_dev_desc = { 161 .clk_required = true, 162 }; 163 164 static struct lpss_shared_clock i2c_clock = { 165 .name = "i2c_clk", 166 .rate = 100000000, 167 }; 168 169 static struct lpss_device_desc byt_i2c_dev_desc = { 170 .clk_required = true, 171 .prv_offset = 0x800, 172 .save_ctx = true, 173 .shared_clock = &i2c_clock, 174 }; 175 176 #else 177 178 #define LPSS_ADDR(desc) (0UL) 179 180 #endif /* CONFIG_X86_INTEL_LPSS */ 181 182 static const struct acpi_device_id acpi_lpss_device_ids[] = { 183 /* Generic LPSS devices */ 184 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 185 186 /* Lynxpoint LPSS devices */ 187 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 188 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 189 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 190 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 191 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 192 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 193 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 194 { "INT33C7", }, 195 196 /* BayTrail LPSS devices */ 197 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 198 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 199 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 200 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 201 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 202 { "INT33B2", }, 203 { "INT33FC", }, 204 205 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 206 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 207 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 208 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 209 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 210 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 211 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 212 { "INT3437", }, 213 214 { } 215 }; 216 217 #ifdef CONFIG_X86_INTEL_LPSS 218 219 static int is_memory(struct acpi_resource *res, void *not_used) 220 { 221 struct resource r; 222 return !acpi_dev_resource_memory(res, &r); 223 } 224 225 /* LPSS main clock device. */ 226 static struct platform_device *lpss_clk_dev; 227 228 static inline void lpt_register_clock_device(void) 229 { 230 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); 231 } 232 233 static int register_device_clock(struct acpi_device *adev, 234 struct lpss_private_data *pdata) 235 { 236 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 237 struct lpss_shared_clock *shared_clock = dev_desc->shared_clock; 238 const char *devname = dev_name(&adev->dev); 239 struct clk *clk = ERR_PTR(-ENODEV); 240 struct lpss_clk_data *clk_data; 241 const char *parent, *clk_name; 242 void __iomem *prv_base; 243 244 if (!lpss_clk_dev) 245 lpt_register_clock_device(); 246 247 clk_data = platform_get_drvdata(lpss_clk_dev); 248 if (!clk_data) 249 return -ENODEV; 250 251 if (dev_desc->clkdev_name) { 252 clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name, 253 devname); 254 return 0; 255 } 256 257 if (!pdata->mmio_base 258 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 259 return -ENODATA; 260 261 parent = clk_data->name; 262 prv_base = pdata->mmio_base + dev_desc->prv_offset; 263 264 if (shared_clock) { 265 clk = shared_clock->clk; 266 if (!clk) { 267 clk = clk_register_fixed_rate(NULL, shared_clock->name, 268 "lpss_clk", 0, 269 shared_clock->rate); 270 shared_clock->clk = clk; 271 } 272 parent = shared_clock->name; 273 } 274 275 if (dev_desc->clk_gate) { 276 clk = clk_register_gate(NULL, devname, parent, 0, 277 prv_base, 0, 0, NULL); 278 parent = devname; 279 } 280 281 if (dev_desc->clk_divider) { 282 /* Prevent division by zero */ 283 if (!readl(prv_base)) 284 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 285 286 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 287 if (!clk_name) 288 return -ENOMEM; 289 clk = clk_register_fractional_divider(NULL, clk_name, parent, 290 0, prv_base, 291 1, 15, 16, 15, 0, NULL); 292 parent = clk_name; 293 294 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 295 if (!clk_name) { 296 kfree(parent); 297 return -ENOMEM; 298 } 299 clk = clk_register_gate(NULL, clk_name, parent, 300 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 301 prv_base, 31, 0, NULL); 302 kfree(parent); 303 kfree(clk_name); 304 } 305 306 if (IS_ERR(clk)) 307 return PTR_ERR(clk); 308 309 pdata->clk = clk; 310 clk_register_clkdev(clk, NULL, devname); 311 return 0; 312 } 313 314 static int acpi_lpss_create_device(struct acpi_device *adev, 315 const struct acpi_device_id *id) 316 { 317 struct lpss_device_desc *dev_desc; 318 struct lpss_private_data *pdata; 319 struct resource_list_entry *rentry; 320 struct list_head resource_list; 321 struct platform_device *pdev; 322 int ret; 323 324 dev_desc = (struct lpss_device_desc *)id->driver_data; 325 if (!dev_desc) { 326 pdev = acpi_create_platform_device(adev); 327 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 328 } 329 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 330 if (!pdata) 331 return -ENOMEM; 332 333 INIT_LIST_HEAD(&resource_list); 334 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 335 if (ret < 0) 336 goto err_out; 337 338 list_for_each_entry(rentry, &resource_list, node) 339 if (resource_type(&rentry->res) == IORESOURCE_MEM) { 340 if (dev_desc->prv_size_override) 341 pdata->mmio_size = dev_desc->prv_size_override; 342 else 343 pdata->mmio_size = resource_size(&rentry->res); 344 pdata->mmio_base = ioremap(rentry->res.start, 345 pdata->mmio_size); 346 break; 347 } 348 349 acpi_dev_free_resource_list(&resource_list); 350 351 pdata->dev_desc = dev_desc; 352 353 if (dev_desc->clk_required) { 354 ret = register_device_clock(adev, pdata); 355 if (ret) { 356 /* Skip the device, but continue the namespace scan. */ 357 ret = 0; 358 goto err_out; 359 } 360 } 361 362 /* 363 * This works around a known issue in ACPI tables where LPSS devices 364 * have _PS0 and _PS3 without _PSC (and no power resources), so 365 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 366 */ 367 ret = acpi_device_fix_up_power(adev); 368 if (ret) { 369 /* Skip the device, but continue the namespace scan. */ 370 ret = 0; 371 goto err_out; 372 } 373 374 if (dev_desc->setup) 375 dev_desc->setup(pdata); 376 377 adev->driver_data = pdata; 378 pdev = acpi_create_platform_device(adev); 379 if (!IS_ERR_OR_NULL(pdev)) { 380 device_enable_async_suspend(&pdev->dev); 381 return 1; 382 } 383 384 ret = PTR_ERR(pdev); 385 adev->driver_data = NULL; 386 387 err_out: 388 kfree(pdata); 389 return ret; 390 } 391 392 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 393 { 394 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 395 } 396 397 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 398 unsigned int reg) 399 { 400 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 401 } 402 403 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 404 { 405 struct acpi_device *adev; 406 struct lpss_private_data *pdata; 407 unsigned long flags; 408 int ret; 409 410 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 411 if (WARN_ON(ret)) 412 return ret; 413 414 spin_lock_irqsave(&dev->power.lock, flags); 415 if (pm_runtime_suspended(dev)) { 416 ret = -EAGAIN; 417 goto out; 418 } 419 pdata = acpi_driver_data(adev); 420 if (WARN_ON(!pdata || !pdata->mmio_base)) { 421 ret = -ENODEV; 422 goto out; 423 } 424 *val = __lpss_reg_read(pdata, reg); 425 426 out: 427 spin_unlock_irqrestore(&dev->power.lock, flags); 428 return ret; 429 } 430 431 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 432 char *buf) 433 { 434 u32 ltr_value = 0; 435 unsigned int reg; 436 int ret; 437 438 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 439 ret = lpss_reg_read(dev, reg, <r_value); 440 if (ret) 441 return ret; 442 443 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 444 } 445 446 static ssize_t lpss_ltr_mode_show(struct device *dev, 447 struct device_attribute *attr, char *buf) 448 { 449 u32 ltr_mode = 0; 450 char *outstr; 451 int ret; 452 453 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 454 if (ret) 455 return ret; 456 457 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 458 return sprintf(buf, "%s\n", outstr); 459 } 460 461 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 462 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 463 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 464 465 static struct attribute *lpss_attrs[] = { 466 &dev_attr_auto_ltr.attr, 467 &dev_attr_sw_ltr.attr, 468 &dev_attr_ltr_mode.attr, 469 NULL, 470 }; 471 472 static struct attribute_group lpss_attr_group = { 473 .attrs = lpss_attrs, 474 .name = "lpss_ltr", 475 }; 476 477 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 478 { 479 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 480 u32 ltr_mode, ltr_val; 481 482 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 483 if (val < 0) { 484 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 485 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 486 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 487 } 488 return; 489 } 490 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 491 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 492 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 493 val = LPSS_LTR_MAX_VAL; 494 } else if (val > LPSS_LTR_MAX_VAL) { 495 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 496 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 497 } else { 498 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 499 } 500 ltr_val |= val; 501 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 502 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 503 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 504 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 505 } 506 } 507 508 #ifdef CONFIG_PM 509 /** 510 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 511 * @dev: LPSS device 512 * 513 * Most LPSS devices have private registers which may loose their context when 514 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 515 * prv_reg_ctx array. 516 */ 517 static void acpi_lpss_save_ctx(struct device *dev) 518 { 519 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 520 unsigned int i; 521 522 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 523 unsigned long offset = i * sizeof(u32); 524 525 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 526 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 527 pdata->prv_reg_ctx[i], offset); 528 } 529 } 530 531 /** 532 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 533 * @dev: LPSS device 534 * 535 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 536 */ 537 static void acpi_lpss_restore_ctx(struct device *dev) 538 { 539 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 540 unsigned int i; 541 542 /* 543 * The following delay is needed or the subsequent write operations may 544 * fail. The LPSS devices are actually PCI devices and the PCI spec 545 * expects 10ms delay before the device can be accessed after D3 to D0 546 * transition. 547 */ 548 msleep(10); 549 550 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 551 unsigned long offset = i * sizeof(u32); 552 553 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 554 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 555 pdata->prv_reg_ctx[i], offset); 556 } 557 } 558 559 #ifdef CONFIG_PM_SLEEP 560 static int acpi_lpss_suspend_late(struct device *dev) 561 { 562 int ret = pm_generic_suspend_late(dev); 563 564 if (ret) 565 return ret; 566 567 acpi_lpss_save_ctx(dev); 568 return acpi_dev_suspend_late(dev); 569 } 570 571 static int acpi_lpss_restore_early(struct device *dev) 572 { 573 int ret = acpi_dev_resume_early(dev); 574 575 if (ret) 576 return ret; 577 578 acpi_lpss_restore_ctx(dev); 579 return pm_generic_resume_early(dev); 580 } 581 #endif /* CONFIG_PM_SLEEP */ 582 583 #ifdef CONFIG_PM_RUNTIME 584 static int acpi_lpss_runtime_suspend(struct device *dev) 585 { 586 int ret = pm_generic_runtime_suspend(dev); 587 588 if (ret) 589 return ret; 590 591 acpi_lpss_save_ctx(dev); 592 return acpi_dev_runtime_suspend(dev); 593 } 594 595 static int acpi_lpss_runtime_resume(struct device *dev) 596 { 597 int ret = acpi_dev_runtime_resume(dev); 598 599 if (ret) 600 return ret; 601 602 acpi_lpss_restore_ctx(dev); 603 return pm_generic_runtime_resume(dev); 604 } 605 #endif /* CONFIG_PM_RUNTIME */ 606 #endif /* CONFIG_PM */ 607 608 static struct dev_pm_domain acpi_lpss_pm_domain = { 609 .ops = { 610 #ifdef CONFIG_PM_SLEEP 611 .suspend_late = acpi_lpss_suspend_late, 612 .restore_early = acpi_lpss_restore_early, 613 .prepare = acpi_subsys_prepare, 614 .complete = acpi_subsys_complete, 615 .suspend = acpi_subsys_suspend, 616 .resume_early = acpi_subsys_resume_early, 617 .freeze = acpi_subsys_freeze, 618 .poweroff = acpi_subsys_suspend, 619 .poweroff_late = acpi_subsys_suspend_late, 620 #endif 621 #ifdef CONFIG_PM_RUNTIME 622 .runtime_suspend = acpi_lpss_runtime_suspend, 623 .runtime_resume = acpi_lpss_runtime_resume, 624 #endif 625 }, 626 }; 627 628 static int acpi_lpss_platform_notify(struct notifier_block *nb, 629 unsigned long action, void *data) 630 { 631 struct platform_device *pdev = to_platform_device(data); 632 struct lpss_private_data *pdata; 633 struct acpi_device *adev; 634 const struct acpi_device_id *id; 635 636 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 637 if (!id || !id->driver_data) 638 return 0; 639 640 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 641 return 0; 642 643 pdata = acpi_driver_data(adev); 644 if (!pdata || !pdata->mmio_base) 645 return 0; 646 647 if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 648 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 649 return 0; 650 } 651 652 switch (action) { 653 case BUS_NOTIFY_BOUND_DRIVER: 654 if (pdata->dev_desc->save_ctx) 655 pdev->dev.pm_domain = &acpi_lpss_pm_domain; 656 break; 657 case BUS_NOTIFY_UNBOUND_DRIVER: 658 if (pdata->dev_desc->save_ctx) 659 pdev->dev.pm_domain = NULL; 660 break; 661 case BUS_NOTIFY_ADD_DEVICE: 662 if (pdata->dev_desc->ltr_required) 663 return sysfs_create_group(&pdev->dev.kobj, 664 &lpss_attr_group); 665 case BUS_NOTIFY_DEL_DEVICE: 666 if (pdata->dev_desc->ltr_required) 667 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 668 default: 669 break; 670 } 671 672 return 0; 673 } 674 675 static struct notifier_block acpi_lpss_nb = { 676 .notifier_call = acpi_lpss_platform_notify, 677 }; 678 679 static void acpi_lpss_bind(struct device *dev) 680 { 681 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 682 683 if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required) 684 return; 685 686 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 687 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 688 else 689 dev_err(dev, "MMIO size insufficient to access LTR\n"); 690 } 691 692 static void acpi_lpss_unbind(struct device *dev) 693 { 694 dev->power.set_latency_tolerance = NULL; 695 } 696 697 static struct acpi_scan_handler lpss_handler = { 698 .ids = acpi_lpss_device_ids, 699 .attach = acpi_lpss_create_device, 700 .bind = acpi_lpss_bind, 701 .unbind = acpi_lpss_unbind, 702 }; 703 704 void __init acpi_lpss_init(void) 705 { 706 if (!lpt_clk_init()) { 707 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 708 acpi_scan_add_handler(&lpss_handler); 709 } 710 } 711 712 #else 713 714 static struct acpi_scan_handler lpss_handler = { 715 .ids = acpi_lpss_device_ids, 716 }; 717 718 void __init acpi_lpss_init(void) 719 { 720 acpi_scan_add_handler(&lpss_handler); 721 } 722 723 #endif /* CONFIG_X86_INTEL_LPSS */ 724