1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ACPI support for Intel Lynxpoint LPSS. 4 * 5 * Copyright (C) 2013, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/dmi.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/platform_device.h> 19 #include <linux/platform_data/x86/clk-lpss.h> 20 #include <linux/platform_data/x86/pmc_atom.h> 21 #include <linux/pm_domain.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pwm.h> 24 #include <linux/suspend.h> 25 #include <linux/delay.h> 26 27 #include "internal.h" 28 29 #ifdef CONFIG_X86_INTEL_LPSS 30 31 #include <asm/cpu_device_id.h> 32 #include <asm/intel-family.h> 33 #include <asm/iosf_mbi.h> 34 35 #define LPSS_ADDR(desc) ((unsigned long)&desc) 36 37 #define LPSS_CLK_SIZE 0x04 38 #define LPSS_LTR_SIZE 0x18 39 40 /* Offsets relative to LPSS_PRIVATE_OFFSET */ 41 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) 42 #define LPSS_RESETS 0x04 43 #define LPSS_RESETS_RESET_FUNC BIT(0) 44 #define LPSS_RESETS_RESET_APB BIT(1) 45 #define LPSS_GENERAL 0x08 46 #define LPSS_GENERAL_LTR_MODE_SW BIT(2) 47 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) 48 #define LPSS_SW_LTR 0x10 49 #define LPSS_AUTO_LTR 0x14 50 #define LPSS_LTR_SNOOP_REQ BIT(15) 51 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF 52 #define LPSS_LTR_SNOOP_LAT_1US 0x800 53 #define LPSS_LTR_SNOOP_LAT_32US 0xC00 54 #define LPSS_LTR_SNOOP_LAT_SHIFT 5 55 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 56 #define LPSS_LTR_MAX_VAL 0x3FF 57 #define LPSS_TX_INT 0x20 58 #define LPSS_TX_INT_MASK BIT(1) 59 60 #define LPSS_PRV_REG_COUNT 9 61 62 /* LPSS Flags */ 63 #define LPSS_CLK BIT(0) 64 #define LPSS_CLK_GATE BIT(1) 65 #define LPSS_CLK_DIVIDER BIT(2) 66 #define LPSS_LTR BIT(3) 67 #define LPSS_SAVE_CTX BIT(4) 68 /* 69 * For some devices the DSDT AML code for another device turns off the device 70 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) 71 * as ctx register values. 72 * Luckily these devices always use the same ctx register values, so we can 73 * work around this by saving the ctx registers once on activation. 74 */ 75 #define LPSS_SAVE_CTX_ONCE BIT(5) 76 #define LPSS_NO_D3_DELAY BIT(6) 77 78 struct lpss_private_data; 79 80 struct lpss_device_desc { 81 unsigned int flags; 82 const char *clk_con_id; 83 unsigned int prv_offset; 84 size_t prv_size_override; 85 struct property_entry *properties; 86 void (*setup)(struct lpss_private_data *pdata); 87 bool resume_from_noirq; 88 }; 89 90 static const struct lpss_device_desc lpss_dma_desc = { 91 .flags = LPSS_CLK, 92 }; 93 94 struct lpss_private_data { 95 struct acpi_device *adev; 96 void __iomem *mmio_base; 97 resource_size_t mmio_size; 98 unsigned int fixed_clk_rate; 99 struct clk *clk; 100 const struct lpss_device_desc *dev_desc; 101 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; 102 }; 103 104 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */ 105 static u32 pmc_atom_d3_mask = 0xfe000ffe; 106 107 /* LPSS run time quirks */ 108 static unsigned int lpss_quirks; 109 110 /* 111 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. 112 * 113 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover 114 * it can be powered off automatically whenever the last LPSS device goes down. 115 * In case of no power any access to the DMA controller will hang the system. 116 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as 117 * well as on ASuS T100TA transformer. 118 * 119 * This quirk overrides power state of entire LPSS island to keep DMA powered 120 * on whenever we have at least one other device in use. 121 */ 122 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) 123 124 /* UART Component Parameter Register */ 125 #define LPSS_UART_CPR 0xF4 126 #define LPSS_UART_CPR_AFCE BIT(4) 127 128 static void lpss_uart_setup(struct lpss_private_data *pdata) 129 { 130 unsigned int offset; 131 u32 val; 132 133 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; 134 val = readl(pdata->mmio_base + offset); 135 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); 136 137 val = readl(pdata->mmio_base + LPSS_UART_CPR); 138 if (!(val & LPSS_UART_CPR_AFCE)) { 139 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; 140 val = readl(pdata->mmio_base + offset); 141 val |= LPSS_GENERAL_UART_RTS_OVRD; 142 writel(val, pdata->mmio_base + offset); 143 } 144 } 145 146 static void lpss_deassert_reset(struct lpss_private_data *pdata) 147 { 148 unsigned int offset; 149 u32 val; 150 151 offset = pdata->dev_desc->prv_offset + LPSS_RESETS; 152 val = readl(pdata->mmio_base + offset); 153 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; 154 writel(val, pdata->mmio_base + offset); 155 } 156 157 /* 158 * BYT PWM used for backlight control by the i915 driver on systems without 159 * the Crystal Cove PMIC. 160 */ 161 static struct pwm_lookup byt_pwm_lookup[] = { 162 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", 163 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 164 "pwm-lpss-platform"), 165 }; 166 167 static void byt_pwm_setup(struct lpss_private_data *pdata) 168 { 169 struct acpi_device *adev = pdata->adev; 170 171 /* Only call pwm_add_table for the first PWM controller */ 172 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 173 return; 174 175 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); 176 } 177 178 #define LPSS_I2C_ENABLE 0x6c 179 180 static void byt_i2c_setup(struct lpss_private_data *pdata) 181 { 182 const char *uid_str = acpi_device_uid(pdata->adev); 183 acpi_handle handle = pdata->adev->handle; 184 unsigned long long shared_host = 0; 185 acpi_status status; 186 long uid = 0; 187 188 /* Expected to always be true, but better safe then sorry */ 189 if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) { 190 /* Detect I2C bus shared with PUNIT and ignore its d3 status */ 191 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); 192 if (ACPI_SUCCESS(status) && shared_host) 193 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1)); 194 } 195 196 lpss_deassert_reset(pdata); 197 198 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) 199 pdata->fixed_clk_rate = 133000000; 200 201 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); 202 } 203 204 /* BSW PWM used for backlight control by the i915 driver */ 205 static struct pwm_lookup bsw_pwm_lookup[] = { 206 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", 207 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL, 208 "pwm-lpss-platform"), 209 }; 210 211 static void bsw_pwm_setup(struct lpss_private_data *pdata) 212 { 213 struct acpi_device *adev = pdata->adev; 214 215 /* Only call pwm_add_table for the first PWM controller */ 216 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) 217 return; 218 219 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); 220 } 221 222 static const struct lpss_device_desc lpt_dev_desc = { 223 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 224 | LPSS_SAVE_CTX, 225 .prv_offset = 0x800, 226 }; 227 228 static const struct lpss_device_desc lpt_i2c_dev_desc = { 229 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX, 230 .prv_offset = 0x800, 231 }; 232 233 static struct property_entry uart_properties[] = { 234 PROPERTY_ENTRY_U32("reg-io-width", 4), 235 PROPERTY_ENTRY_U32("reg-shift", 2), 236 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), 237 { }, 238 }; 239 240 static const struct lpss_device_desc lpt_uart_dev_desc = { 241 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR 242 | LPSS_SAVE_CTX, 243 .clk_con_id = "baudclk", 244 .prv_offset = 0x800, 245 .setup = lpss_uart_setup, 246 .properties = uart_properties, 247 }; 248 249 static const struct lpss_device_desc lpt_sdio_dev_desc = { 250 .flags = LPSS_LTR, 251 .prv_offset = 0x1000, 252 .prv_size_override = 0x1018, 253 }; 254 255 static const struct lpss_device_desc byt_pwm_dev_desc = { 256 .flags = LPSS_SAVE_CTX, 257 .prv_offset = 0x800, 258 .setup = byt_pwm_setup, 259 }; 260 261 static const struct lpss_device_desc bsw_pwm_dev_desc = { 262 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, 263 .prv_offset = 0x800, 264 .setup = bsw_pwm_setup, 265 .resume_from_noirq = true, 266 }; 267 268 static const struct lpss_device_desc byt_uart_dev_desc = { 269 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 270 .clk_con_id = "baudclk", 271 .prv_offset = 0x800, 272 .setup = lpss_uart_setup, 273 .properties = uart_properties, 274 }; 275 276 static const struct lpss_device_desc bsw_uart_dev_desc = { 277 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 278 | LPSS_NO_D3_DELAY, 279 .clk_con_id = "baudclk", 280 .prv_offset = 0x800, 281 .setup = lpss_uart_setup, 282 .properties = uart_properties, 283 }; 284 285 static const struct lpss_device_desc byt_spi_dev_desc = { 286 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, 287 .prv_offset = 0x400, 288 }; 289 290 static const struct lpss_device_desc byt_sdio_dev_desc = { 291 .flags = LPSS_CLK, 292 }; 293 294 static const struct lpss_device_desc byt_i2c_dev_desc = { 295 .flags = LPSS_CLK | LPSS_SAVE_CTX, 296 .prv_offset = 0x800, 297 .setup = byt_i2c_setup, 298 .resume_from_noirq = true, 299 }; 300 301 static const struct lpss_device_desc bsw_i2c_dev_desc = { 302 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, 303 .prv_offset = 0x800, 304 .setup = byt_i2c_setup, 305 .resume_from_noirq = true, 306 }; 307 308 static const struct lpss_device_desc bsw_spi_dev_desc = { 309 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX 310 | LPSS_NO_D3_DELAY, 311 .prv_offset = 0x400, 312 .setup = lpss_deassert_reset, 313 }; 314 315 static const struct x86_cpu_id lpss_cpu_ids[] = { 316 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL), 317 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL), 318 {} 319 }; 320 321 #else 322 323 #define LPSS_ADDR(desc) (0UL) 324 325 #endif /* CONFIG_X86_INTEL_LPSS */ 326 327 static const struct acpi_device_id acpi_lpss_device_ids[] = { 328 /* Generic LPSS devices */ 329 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, 330 331 /* Lynxpoint LPSS devices */ 332 { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, 333 { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, 334 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, 335 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, 336 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, 337 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, 338 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, 339 { "INT33C7", }, 340 341 /* BayTrail LPSS devices */ 342 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, 343 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, 344 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, 345 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, 346 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, 347 { "INT33B2", }, 348 { "INT33FC", }, 349 350 /* Braswell LPSS devices */ 351 { "80862286", LPSS_ADDR(lpss_dma_desc) }, 352 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, 353 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, 354 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, 355 { "808622C0", LPSS_ADDR(lpss_dma_desc) }, 356 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, 357 358 /* Broadwell LPSS devices */ 359 { "INT3430", LPSS_ADDR(lpt_dev_desc) }, 360 { "INT3431", LPSS_ADDR(lpt_dev_desc) }, 361 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, 362 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, 363 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, 364 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, 365 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, 366 { "INT3437", }, 367 368 /* Wildcat Point LPSS devices */ 369 { "INT3438", LPSS_ADDR(lpt_dev_desc) }, 370 371 { } 372 }; 373 374 #ifdef CONFIG_X86_INTEL_LPSS 375 376 static int is_memory(struct acpi_resource *res, void *not_used) 377 { 378 struct resource r; 379 380 return !acpi_dev_resource_memory(res, &r); 381 } 382 383 /* LPSS main clock device. */ 384 static struct platform_device *lpss_clk_dev; 385 386 static inline void lpt_register_clock_device(void) 387 { 388 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom", 389 PLATFORM_DEVID_NONE, 390 NULL, 0); 391 } 392 393 static int register_device_clock(struct acpi_device *adev, 394 struct lpss_private_data *pdata) 395 { 396 const struct lpss_device_desc *dev_desc = pdata->dev_desc; 397 const char *devname = dev_name(&adev->dev); 398 struct clk *clk; 399 struct lpss_clk_data *clk_data; 400 const char *parent, *clk_name; 401 void __iomem *prv_base; 402 403 if (!lpss_clk_dev) 404 lpt_register_clock_device(); 405 406 clk_data = platform_get_drvdata(lpss_clk_dev); 407 if (!clk_data) 408 return -ENODEV; 409 clk = clk_data->clk; 410 411 if (!pdata->mmio_base 412 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) 413 return -ENODATA; 414 415 parent = clk_data->name; 416 prv_base = pdata->mmio_base + dev_desc->prv_offset; 417 418 if (pdata->fixed_clk_rate) { 419 clk = clk_register_fixed_rate(NULL, devname, parent, 0, 420 pdata->fixed_clk_rate); 421 goto out; 422 } 423 424 if (dev_desc->flags & LPSS_CLK_GATE) { 425 clk = clk_register_gate(NULL, devname, parent, 0, 426 prv_base, 0, 0, NULL); 427 parent = devname; 428 } 429 430 if (dev_desc->flags & LPSS_CLK_DIVIDER) { 431 /* Prevent division by zero */ 432 if (!readl(prv_base)) 433 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); 434 435 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); 436 if (!clk_name) 437 return -ENOMEM; 438 clk = clk_register_fractional_divider(NULL, clk_name, parent, 439 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS, 440 prv_base, 1, 15, 16, 15, 0, NULL); 441 parent = clk_name; 442 443 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); 444 if (!clk_name) { 445 kfree(parent); 446 return -ENOMEM; 447 } 448 clk = clk_register_gate(NULL, clk_name, parent, 449 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, 450 prv_base, 31, 0, NULL); 451 kfree(parent); 452 kfree(clk_name); 453 } 454 out: 455 if (IS_ERR(clk)) 456 return PTR_ERR(clk); 457 458 pdata->clk = clk; 459 clk_register_clkdev(clk, dev_desc->clk_con_id, devname); 460 return 0; 461 } 462 463 struct lpss_device_links { 464 const char *supplier_hid; 465 const char *supplier_uid; 466 const char *consumer_hid; 467 const char *consumer_uid; 468 u32 flags; 469 const struct dmi_system_id *dep_missing_ids; 470 }; 471 472 /* Please keep this list sorted alphabetically by vendor and model */ 473 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = { 474 { 475 .matches = { 476 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 477 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"), 478 }, 479 }, 480 {} 481 }; 482 483 /* 484 * The _DEP method is used to identify dependencies but instead of creating 485 * device links for every handle in _DEP, only links in the following list are 486 * created. That is necessary because, in the general case, _DEP can refer to 487 * devices that might not have drivers, or that are on different buses, or where 488 * the supplier is not enumerated until after the consumer is probed. 489 */ 490 static const struct lpss_device_links lpss_device_links[] = { 491 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */ 492 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME}, 493 /* CHT iGPU depends on PMIC I2C controller */ 494 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 495 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */ 496 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME, 497 i2c1_dep_missing_dmi_ids}, 498 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */ 499 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 500 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */ 501 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME}, 502 }; 503 504 static bool acpi_lpss_is_supplier(struct acpi_device *adev, 505 const struct lpss_device_links *link) 506 { 507 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid); 508 } 509 510 static bool acpi_lpss_is_consumer(struct acpi_device *adev, 511 const struct lpss_device_links *link) 512 { 513 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid); 514 } 515 516 struct hid_uid { 517 const char *hid; 518 const char *uid; 519 }; 520 521 static int match_hid_uid(struct device *dev, const void *data) 522 { 523 struct acpi_device *adev = ACPI_COMPANION(dev); 524 const struct hid_uid *id = data; 525 526 if (!adev) 527 return 0; 528 529 return acpi_dev_hid_uid_match(adev, id->hid, id->uid); 530 } 531 532 static struct device *acpi_lpss_find_device(const char *hid, const char *uid) 533 { 534 struct device *dev; 535 536 struct hid_uid data = { 537 .hid = hid, 538 .uid = uid, 539 }; 540 541 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid); 542 if (dev) 543 return dev; 544 545 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid); 546 } 547 548 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle) 549 { 550 struct acpi_handle_list dep_devices; 551 acpi_status status; 552 int i; 553 554 if (!acpi_has_method(adev->handle, "_DEP")) 555 return false; 556 557 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL, 558 &dep_devices); 559 if (ACPI_FAILURE(status)) { 560 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n"); 561 return false; 562 } 563 564 for (i = 0; i < dep_devices.count; i++) { 565 if (dep_devices.handles[i] == handle) 566 return true; 567 } 568 569 return false; 570 } 571 572 static void acpi_lpss_link_consumer(struct device *dev1, 573 const struct lpss_device_links *link) 574 { 575 struct device *dev2; 576 577 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid); 578 if (!dev2) 579 return; 580 581 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 582 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1))) 583 device_link_add(dev2, dev1, link->flags); 584 585 put_device(dev2); 586 } 587 588 static void acpi_lpss_link_supplier(struct device *dev1, 589 const struct lpss_device_links *link) 590 { 591 struct device *dev2; 592 593 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid); 594 if (!dev2) 595 return; 596 597 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids)) 598 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2))) 599 device_link_add(dev1, dev2, link->flags); 600 601 put_device(dev2); 602 } 603 604 static void acpi_lpss_create_device_links(struct acpi_device *adev, 605 struct platform_device *pdev) 606 { 607 int i; 608 609 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) { 610 const struct lpss_device_links *link = &lpss_device_links[i]; 611 612 if (acpi_lpss_is_supplier(adev, link)) 613 acpi_lpss_link_consumer(&pdev->dev, link); 614 615 if (acpi_lpss_is_consumer(adev, link)) 616 acpi_lpss_link_supplier(&pdev->dev, link); 617 } 618 } 619 620 static int acpi_lpss_create_device(struct acpi_device *adev, 621 const struct acpi_device_id *id) 622 { 623 const struct lpss_device_desc *dev_desc; 624 struct lpss_private_data *pdata; 625 struct resource_entry *rentry; 626 struct list_head resource_list; 627 struct platform_device *pdev; 628 int ret; 629 630 dev_desc = (const struct lpss_device_desc *)id->driver_data; 631 if (!dev_desc) { 632 pdev = acpi_create_platform_device(adev, NULL); 633 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; 634 } 635 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 636 if (!pdata) 637 return -ENOMEM; 638 639 INIT_LIST_HEAD(&resource_list); 640 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); 641 if (ret < 0) 642 goto err_out; 643 644 list_for_each_entry(rentry, &resource_list, node) 645 if (resource_type(rentry->res) == IORESOURCE_MEM) { 646 if (dev_desc->prv_size_override) 647 pdata->mmio_size = dev_desc->prv_size_override; 648 else 649 pdata->mmio_size = resource_size(rentry->res); 650 pdata->mmio_base = ioremap(rentry->res->start, 651 pdata->mmio_size); 652 break; 653 } 654 655 acpi_dev_free_resource_list(&resource_list); 656 657 if (!pdata->mmio_base) { 658 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ 659 adev->pnp.type.platform_id = 0; 660 /* Skip the device, but continue the namespace scan. */ 661 ret = 0; 662 goto err_out; 663 } 664 665 pdata->adev = adev; 666 pdata->dev_desc = dev_desc; 667 668 if (dev_desc->setup) 669 dev_desc->setup(pdata); 670 671 if (dev_desc->flags & LPSS_CLK) { 672 ret = register_device_clock(adev, pdata); 673 if (ret) { 674 /* Skip the device, but continue the namespace scan. */ 675 ret = 0; 676 goto err_out; 677 } 678 } 679 680 /* 681 * This works around a known issue in ACPI tables where LPSS devices 682 * have _PS0 and _PS3 without _PSC (and no power resources), so 683 * acpi_bus_init_power() will assume that the BIOS has put them into D0. 684 */ 685 acpi_device_fix_up_power(adev); 686 687 adev->driver_data = pdata; 688 pdev = acpi_create_platform_device(adev, dev_desc->properties); 689 if (!IS_ERR_OR_NULL(pdev)) { 690 acpi_lpss_create_device_links(adev, pdev); 691 return 1; 692 } 693 694 ret = PTR_ERR(pdev); 695 adev->driver_data = NULL; 696 697 err_out: 698 kfree(pdata); 699 return ret; 700 } 701 702 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) 703 { 704 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 705 } 706 707 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, 708 unsigned int reg) 709 { 710 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); 711 } 712 713 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) 714 { 715 struct acpi_device *adev; 716 struct lpss_private_data *pdata; 717 unsigned long flags; 718 int ret; 719 720 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); 721 if (WARN_ON(ret)) 722 return ret; 723 724 spin_lock_irqsave(&dev->power.lock, flags); 725 if (pm_runtime_suspended(dev)) { 726 ret = -EAGAIN; 727 goto out; 728 } 729 pdata = acpi_driver_data(adev); 730 if (WARN_ON(!pdata || !pdata->mmio_base)) { 731 ret = -ENODEV; 732 goto out; 733 } 734 *val = __lpss_reg_read(pdata, reg); 735 736 out: 737 spin_unlock_irqrestore(&dev->power.lock, flags); 738 return ret; 739 } 740 741 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, 742 char *buf) 743 { 744 u32 ltr_value = 0; 745 unsigned int reg; 746 int ret; 747 748 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; 749 ret = lpss_reg_read(dev, reg, <r_value); 750 if (ret) 751 return ret; 752 753 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); 754 } 755 756 static ssize_t lpss_ltr_mode_show(struct device *dev, 757 struct device_attribute *attr, char *buf) 758 { 759 u32 ltr_mode = 0; 760 char *outstr; 761 int ret; 762 763 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); 764 if (ret) 765 return ret; 766 767 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; 768 return sprintf(buf, "%s\n", outstr); 769 } 770 771 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); 772 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); 773 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); 774 775 static struct attribute *lpss_attrs[] = { 776 &dev_attr_auto_ltr.attr, 777 &dev_attr_sw_ltr.attr, 778 &dev_attr_ltr_mode.attr, 779 NULL, 780 }; 781 782 static const struct attribute_group lpss_attr_group = { 783 .attrs = lpss_attrs, 784 .name = "lpss_ltr", 785 }; 786 787 static void acpi_lpss_set_ltr(struct device *dev, s32 val) 788 { 789 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 790 u32 ltr_mode, ltr_val; 791 792 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); 793 if (val < 0) { 794 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { 795 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; 796 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 797 } 798 return; 799 } 800 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; 801 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { 802 ltr_val |= LPSS_LTR_SNOOP_LAT_32US; 803 val = LPSS_LTR_MAX_VAL; 804 } else if (val > LPSS_LTR_MAX_VAL) { 805 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; 806 val >>= LPSS_LTR_SNOOP_LAT_SHIFT; 807 } else { 808 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; 809 } 810 ltr_val |= val; 811 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); 812 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { 813 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; 814 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); 815 } 816 } 817 818 #ifdef CONFIG_PM 819 /** 820 * acpi_lpss_save_ctx() - Save the private registers of LPSS device 821 * @dev: LPSS device 822 * @pdata: pointer to the private data of the LPSS device 823 * 824 * Most LPSS devices have private registers which may loose their context when 825 * the device is powered down. acpi_lpss_save_ctx() saves those registers into 826 * prv_reg_ctx array. 827 */ 828 static void acpi_lpss_save_ctx(struct device *dev, 829 struct lpss_private_data *pdata) 830 { 831 unsigned int i; 832 833 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 834 unsigned long offset = i * sizeof(u32); 835 836 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); 837 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", 838 pdata->prv_reg_ctx[i], offset); 839 } 840 } 841 842 /** 843 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device 844 * @dev: LPSS device 845 * @pdata: pointer to the private data of the LPSS device 846 * 847 * Restores the registers that were previously stored with acpi_lpss_save_ctx(). 848 */ 849 static void acpi_lpss_restore_ctx(struct device *dev, 850 struct lpss_private_data *pdata) 851 { 852 unsigned int i; 853 854 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { 855 unsigned long offset = i * sizeof(u32); 856 857 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); 858 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", 859 pdata->prv_reg_ctx[i], offset); 860 } 861 } 862 863 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) 864 { 865 /* 866 * The following delay is needed or the subsequent write operations may 867 * fail. The LPSS devices are actually PCI devices and the PCI spec 868 * expects 10ms delay before the device can be accessed after D3 to D0 869 * transition. However some platforms like BSW does not need this delay. 870 */ 871 unsigned int delay = 10; /* default 10ms delay */ 872 873 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) 874 delay = 0; 875 876 msleep(delay); 877 } 878 879 static int acpi_lpss_activate(struct device *dev) 880 { 881 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 882 int ret; 883 884 ret = acpi_dev_resume(dev); 885 if (ret) 886 return ret; 887 888 acpi_lpss_d3_to_d0_delay(pdata); 889 890 /* 891 * This is called only on ->probe() stage where a device is either in 892 * known state defined by BIOS or most likely powered off. Due to this 893 * we have to deassert reset line to be sure that ->probe() will 894 * recognize the device. 895 */ 896 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 897 lpss_deassert_reset(pdata); 898 899 #ifdef CONFIG_PM 900 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) 901 acpi_lpss_save_ctx(dev, pdata); 902 #endif 903 904 return 0; 905 } 906 907 static void acpi_lpss_dismiss(struct device *dev) 908 { 909 acpi_dev_suspend(dev, false); 910 } 911 912 /* IOSF SB for LPSS island */ 913 #define LPSS_IOSF_UNIT_LPIOEP 0xA0 914 #define LPSS_IOSF_UNIT_LPIO1 0xAB 915 #define LPSS_IOSF_UNIT_LPIO2 0xAC 916 917 #define LPSS_IOSF_PMCSR 0x84 918 #define LPSS_PMCSR_D0 0 919 #define LPSS_PMCSR_D3hot 3 920 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) 921 922 #define LPSS_IOSF_GPIODEF0 0x154 923 #define LPSS_GPIODEF0_DMA1_D3 BIT(2) 924 #define LPSS_GPIODEF0_DMA2_D3 BIT(3) 925 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) 926 #define LPSS_GPIODEF0_DMA_LLP BIT(13) 927 928 static DEFINE_MUTEX(lpss_iosf_mutex); 929 static bool lpss_iosf_d3_entered = true; 930 931 static void lpss_iosf_enter_d3_state(void) 932 { 933 u32 value1 = 0; 934 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 935 u32 value2 = LPSS_PMCSR_D3hot; 936 u32 mask2 = LPSS_PMCSR_Dx_MASK; 937 /* 938 * PMC provides an information about actual status of the LPSS devices. 939 * Here we read the values related to LPSS power island, i.e. LPSS 940 * devices, excluding both LPSS DMA controllers, along with SCC domain. 941 */ 942 u32 func_dis, d3_sts_0, pmc_status; 943 int ret; 944 945 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); 946 if (ret) 947 return; 948 949 mutex_lock(&lpss_iosf_mutex); 950 951 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); 952 if (ret) 953 goto exit; 954 955 /* 956 * Get the status of entire LPSS power island per device basis. 957 * Shutdown both LPSS DMA controllers if and only if all other devices 958 * are already in D3hot. 959 */ 960 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask; 961 if (pmc_status) 962 goto exit; 963 964 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 965 LPSS_IOSF_PMCSR, value2, mask2); 966 967 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 968 LPSS_IOSF_PMCSR, value2, mask2); 969 970 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 971 LPSS_IOSF_GPIODEF0, value1, mask1); 972 973 lpss_iosf_d3_entered = true; 974 975 exit: 976 mutex_unlock(&lpss_iosf_mutex); 977 } 978 979 static void lpss_iosf_exit_d3_state(void) 980 { 981 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | 982 LPSS_GPIODEF0_DMA_LLP; 983 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; 984 u32 value2 = LPSS_PMCSR_D0; 985 u32 mask2 = LPSS_PMCSR_Dx_MASK; 986 987 mutex_lock(&lpss_iosf_mutex); 988 989 if (!lpss_iosf_d3_entered) 990 goto exit; 991 992 lpss_iosf_d3_entered = false; 993 994 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, 995 LPSS_IOSF_GPIODEF0, value1, mask1); 996 997 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, 998 LPSS_IOSF_PMCSR, value2, mask2); 999 1000 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, 1001 LPSS_IOSF_PMCSR, value2, mask2); 1002 1003 exit: 1004 mutex_unlock(&lpss_iosf_mutex); 1005 } 1006 1007 static int acpi_lpss_suspend(struct device *dev, bool wakeup) 1008 { 1009 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1010 int ret; 1011 1012 if (pdata->dev_desc->flags & LPSS_SAVE_CTX) 1013 acpi_lpss_save_ctx(dev, pdata); 1014 1015 ret = acpi_dev_suspend(dev, wakeup); 1016 1017 /* 1018 * This call must be last in the sequence, otherwise PMC will return 1019 * wrong status for devices being about to be powered off. See 1020 * lpss_iosf_enter_d3_state() for further information. 1021 */ 1022 if (acpi_target_system_state() == ACPI_STATE_S0 && 1023 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1024 lpss_iosf_enter_d3_state(); 1025 1026 return ret; 1027 } 1028 1029 static int acpi_lpss_resume(struct device *dev) 1030 { 1031 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1032 int ret; 1033 1034 /* 1035 * This call is kept first to be in symmetry with 1036 * acpi_lpss_runtime_suspend() one. 1037 */ 1038 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) 1039 lpss_iosf_exit_d3_state(); 1040 1041 ret = acpi_dev_resume(dev); 1042 if (ret) 1043 return ret; 1044 1045 acpi_lpss_d3_to_d0_delay(pdata); 1046 1047 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) 1048 acpi_lpss_restore_ctx(dev, pdata); 1049 1050 return 0; 1051 } 1052 1053 #ifdef CONFIG_PM_SLEEP 1054 static int acpi_lpss_do_suspend_late(struct device *dev) 1055 { 1056 int ret; 1057 1058 if (dev_pm_skip_suspend(dev)) 1059 return 0; 1060 1061 ret = pm_generic_suspend_late(dev); 1062 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1063 } 1064 1065 static int acpi_lpss_suspend_late(struct device *dev) 1066 { 1067 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1068 1069 if (pdata->dev_desc->resume_from_noirq) 1070 return 0; 1071 1072 return acpi_lpss_do_suspend_late(dev); 1073 } 1074 1075 static int acpi_lpss_suspend_noirq(struct device *dev) 1076 { 1077 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1078 int ret; 1079 1080 if (pdata->dev_desc->resume_from_noirq) { 1081 /* 1082 * The driver's ->suspend_late callback will be invoked by 1083 * acpi_lpss_do_suspend_late(), with the assumption that the 1084 * driver really wanted to run that code in ->suspend_noirq, but 1085 * it could not run after acpi_dev_suspend() and the driver 1086 * expected the latter to be called in the "late" phase. 1087 */ 1088 ret = acpi_lpss_do_suspend_late(dev); 1089 if (ret) 1090 return ret; 1091 } 1092 1093 return acpi_subsys_suspend_noirq(dev); 1094 } 1095 1096 static int acpi_lpss_do_resume_early(struct device *dev) 1097 { 1098 int ret = acpi_lpss_resume(dev); 1099 1100 return ret ? ret : pm_generic_resume_early(dev); 1101 } 1102 1103 static int acpi_lpss_resume_early(struct device *dev) 1104 { 1105 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1106 1107 if (pdata->dev_desc->resume_from_noirq) 1108 return 0; 1109 1110 if (dev_pm_skip_resume(dev)) 1111 return 0; 1112 1113 return acpi_lpss_do_resume_early(dev); 1114 } 1115 1116 static int acpi_lpss_resume_noirq(struct device *dev) 1117 { 1118 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1119 int ret; 1120 1121 /* Follow acpi_subsys_resume_noirq(). */ 1122 if (dev_pm_skip_resume(dev)) 1123 return 0; 1124 1125 ret = pm_generic_resume_noirq(dev); 1126 if (ret) 1127 return ret; 1128 1129 if (!pdata->dev_desc->resume_from_noirq) 1130 return 0; 1131 1132 /* 1133 * The driver's ->resume_early callback will be invoked by 1134 * acpi_lpss_do_resume_early(), with the assumption that the driver 1135 * really wanted to run that code in ->resume_noirq, but it could not 1136 * run before acpi_dev_resume() and the driver expected the latter to be 1137 * called in the "early" phase. 1138 */ 1139 return acpi_lpss_do_resume_early(dev); 1140 } 1141 1142 static int acpi_lpss_do_restore_early(struct device *dev) 1143 { 1144 int ret = acpi_lpss_resume(dev); 1145 1146 return ret ? ret : pm_generic_restore_early(dev); 1147 } 1148 1149 static int acpi_lpss_restore_early(struct device *dev) 1150 { 1151 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1152 1153 if (pdata->dev_desc->resume_from_noirq) 1154 return 0; 1155 1156 return acpi_lpss_do_restore_early(dev); 1157 } 1158 1159 static int acpi_lpss_restore_noirq(struct device *dev) 1160 { 1161 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1162 int ret; 1163 1164 ret = pm_generic_restore_noirq(dev); 1165 if (ret) 1166 return ret; 1167 1168 if (!pdata->dev_desc->resume_from_noirq) 1169 return 0; 1170 1171 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */ 1172 return acpi_lpss_do_restore_early(dev); 1173 } 1174 1175 static int acpi_lpss_do_poweroff_late(struct device *dev) 1176 { 1177 int ret = pm_generic_poweroff_late(dev); 1178 1179 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); 1180 } 1181 1182 static int acpi_lpss_poweroff_late(struct device *dev) 1183 { 1184 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1185 1186 if (dev_pm_skip_suspend(dev)) 1187 return 0; 1188 1189 if (pdata->dev_desc->resume_from_noirq) 1190 return 0; 1191 1192 return acpi_lpss_do_poweroff_late(dev); 1193 } 1194 1195 static int acpi_lpss_poweroff_noirq(struct device *dev) 1196 { 1197 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1198 1199 if (dev_pm_skip_suspend(dev)) 1200 return 0; 1201 1202 if (pdata->dev_desc->resume_from_noirq) { 1203 /* This is analogous to the acpi_lpss_suspend_noirq() case. */ 1204 int ret = acpi_lpss_do_poweroff_late(dev); 1205 1206 if (ret) 1207 return ret; 1208 } 1209 1210 return pm_generic_poweroff_noirq(dev); 1211 } 1212 #endif /* CONFIG_PM_SLEEP */ 1213 1214 static int acpi_lpss_runtime_suspend(struct device *dev) 1215 { 1216 int ret = pm_generic_runtime_suspend(dev); 1217 1218 return ret ? ret : acpi_lpss_suspend(dev, true); 1219 } 1220 1221 static int acpi_lpss_runtime_resume(struct device *dev) 1222 { 1223 int ret = acpi_lpss_resume(dev); 1224 1225 return ret ? ret : pm_generic_runtime_resume(dev); 1226 } 1227 #endif /* CONFIG_PM */ 1228 1229 static struct dev_pm_domain acpi_lpss_pm_domain = { 1230 #ifdef CONFIG_PM 1231 .activate = acpi_lpss_activate, 1232 .dismiss = acpi_lpss_dismiss, 1233 #endif 1234 .ops = { 1235 #ifdef CONFIG_PM 1236 #ifdef CONFIG_PM_SLEEP 1237 .prepare = acpi_subsys_prepare, 1238 .complete = acpi_subsys_complete, 1239 .suspend = acpi_subsys_suspend, 1240 .suspend_late = acpi_lpss_suspend_late, 1241 .suspend_noirq = acpi_lpss_suspend_noirq, 1242 .resume_noirq = acpi_lpss_resume_noirq, 1243 .resume_early = acpi_lpss_resume_early, 1244 .freeze = acpi_subsys_freeze, 1245 .poweroff = acpi_subsys_poweroff, 1246 .poweroff_late = acpi_lpss_poweroff_late, 1247 .poweroff_noirq = acpi_lpss_poweroff_noirq, 1248 .restore_noirq = acpi_lpss_restore_noirq, 1249 .restore_early = acpi_lpss_restore_early, 1250 #endif 1251 .runtime_suspend = acpi_lpss_runtime_suspend, 1252 .runtime_resume = acpi_lpss_runtime_resume, 1253 #endif 1254 }, 1255 }; 1256 1257 static int acpi_lpss_platform_notify(struct notifier_block *nb, 1258 unsigned long action, void *data) 1259 { 1260 struct platform_device *pdev = to_platform_device(data); 1261 struct lpss_private_data *pdata; 1262 struct acpi_device *adev; 1263 const struct acpi_device_id *id; 1264 1265 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); 1266 if (!id || !id->driver_data) 1267 return 0; 1268 1269 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) 1270 return 0; 1271 1272 pdata = acpi_driver_data(adev); 1273 if (!pdata) 1274 return 0; 1275 1276 if (pdata->mmio_base && 1277 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { 1278 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); 1279 return 0; 1280 } 1281 1282 switch (action) { 1283 case BUS_NOTIFY_BIND_DRIVER: 1284 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1285 break; 1286 case BUS_NOTIFY_DRIVER_NOT_BOUND: 1287 case BUS_NOTIFY_UNBOUND_DRIVER: 1288 dev_pm_domain_set(&pdev->dev, NULL); 1289 break; 1290 case BUS_NOTIFY_ADD_DEVICE: 1291 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); 1292 if (pdata->dev_desc->flags & LPSS_LTR) 1293 return sysfs_create_group(&pdev->dev.kobj, 1294 &lpss_attr_group); 1295 break; 1296 case BUS_NOTIFY_DEL_DEVICE: 1297 if (pdata->dev_desc->flags & LPSS_LTR) 1298 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); 1299 dev_pm_domain_set(&pdev->dev, NULL); 1300 break; 1301 default: 1302 break; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static struct notifier_block acpi_lpss_nb = { 1309 .notifier_call = acpi_lpss_platform_notify, 1310 }; 1311 1312 static void acpi_lpss_bind(struct device *dev) 1313 { 1314 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); 1315 1316 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) 1317 return; 1318 1319 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) 1320 dev->power.set_latency_tolerance = acpi_lpss_set_ltr; 1321 else 1322 dev_err(dev, "MMIO size insufficient to access LTR\n"); 1323 } 1324 1325 static void acpi_lpss_unbind(struct device *dev) 1326 { 1327 dev->power.set_latency_tolerance = NULL; 1328 } 1329 1330 static struct acpi_scan_handler lpss_handler = { 1331 .ids = acpi_lpss_device_ids, 1332 .attach = acpi_lpss_create_device, 1333 .bind = acpi_lpss_bind, 1334 .unbind = acpi_lpss_unbind, 1335 }; 1336 1337 void __init acpi_lpss_init(void) 1338 { 1339 const struct x86_cpu_id *id; 1340 int ret; 1341 1342 ret = lpss_atom_clk_init(); 1343 if (ret) 1344 return; 1345 1346 id = x86_match_cpu(lpss_cpu_ids); 1347 if (id) 1348 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; 1349 1350 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); 1351 acpi_scan_add_handler(&lpss_handler); 1352 } 1353 1354 #else 1355 1356 static struct acpi_scan_handler lpss_handler = { 1357 .ids = acpi_lpss_device_ids, 1358 }; 1359 1360 void __init acpi_lpss_init(void) 1361 { 1362 acpi_scan_add_handler(&lpss_handler); 1363 } 1364 1365 #endif /* CONFIG_X86_INTEL_LPSS */ 1366