1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include "ivpu_drv.h" 7 #include "ivpu_fw.h" 8 #include "ivpu_hw_37xx_reg.h" 9 #include "ivpu_hw_reg_io.h" 10 #include "ivpu_hw.h" 11 #include "ivpu_ipc.h" 12 #include "ivpu_mmu.h" 13 #include "ivpu_pm.h" 14 15 #define TILE_FUSE_ENABLE_BOTH 0x0 16 #define TILE_SKU_BOTH_MTL 0x3630 17 18 /* Work point configuration values */ 19 #define CONFIG_1_TILE 0x01 20 #define CONFIG_2_TILE 0x02 21 #define PLL_RATIO_5_3 0x01 22 #define PLL_RATIO_4_3 0x02 23 #define WP_CONFIG(tile, ratio) (((tile) << 8) | (ratio)) 24 #define WP_CONFIG_1_TILE_5_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_5_3) 25 #define WP_CONFIG_1_TILE_4_3_RATIO WP_CONFIG(CONFIG_1_TILE, PLL_RATIO_4_3) 26 #define WP_CONFIG_2_TILE_5_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_5_3) 27 #define WP_CONFIG_2_TILE_4_3_RATIO WP_CONFIG(CONFIG_2_TILE, PLL_RATIO_4_3) 28 #define WP_CONFIG_0_TILE_PLL_OFF WP_CONFIG(0, 0) 29 30 #define PLL_REF_CLK_FREQ (50 * 1000000) 31 #define PLL_SIMULATION_FREQ (10 * 1000000) 32 #define PLL_DEFAULT_EPP_VALUE 0x80 33 34 #define TIM_SAFE_ENABLE 0xf1d0dead 35 #define TIM_WATCHDOG_RESET_VALUE 0xffffffff 36 37 #define TIMEOUT_US (150 * USEC_PER_MSEC) 38 #define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC) 39 #define PLL_TIMEOUT_US (1500 * USEC_PER_MSEC) 40 #define IDLE_TIMEOUT_US (500 * USEC_PER_MSEC) 41 42 #define ICB_0_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ 43 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ 44 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ 45 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ 46 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ 47 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ 48 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) 49 50 #define ICB_1_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ 51 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ 52 (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) 53 54 #define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK) 55 56 #define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)) | \ 57 (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \ 58 (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR))) 59 60 #define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK) 61 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1) 62 63 #define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ 64 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ 65 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ 66 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ 67 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ 68 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ 69 (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) 70 71 static char *ivpu_platform_to_str(u32 platform) 72 { 73 switch (platform) { 74 case IVPU_PLATFORM_SILICON: 75 return "IVPU_PLATFORM_SILICON"; 76 case IVPU_PLATFORM_SIMICS: 77 return "IVPU_PLATFORM_SIMICS"; 78 case IVPU_PLATFORM_FPGA: 79 return "IVPU_PLATFORM_FPGA"; 80 default: 81 return "Invalid platform"; 82 } 83 } 84 85 static void ivpu_hw_read_platform(struct ivpu_device *vdev) 86 { 87 u32 gen_ctrl = REGV_RD32(VPU_37XX_HOST_SS_GEN_CTRL); 88 u32 platform = REG_GET_FLD(VPU_37XX_HOST_SS_GEN_CTRL, PS, gen_ctrl); 89 90 if (platform == IVPU_PLATFORM_SIMICS || platform == IVPU_PLATFORM_FPGA) 91 vdev->platform = platform; 92 else 93 vdev->platform = IVPU_PLATFORM_SILICON; 94 95 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", 96 ivpu_platform_to_str(vdev->platform), vdev->platform); 97 } 98 99 static void ivpu_hw_wa_init(struct ivpu_device *vdev) 100 { 101 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); 102 vdev->wa.clear_runtime_mem = false; 103 vdev->wa.d3hot_after_power_off = true; 104 105 if (ivpu_device_id(vdev) == PCI_DEVICE_ID_MTL && ivpu_revision(vdev) < 4) 106 vdev->wa.interrupt_clear_with_0 = true; 107 } 108 109 static void ivpu_hw_timeouts_init(struct ivpu_device *vdev) 110 { 111 if (ivpu_is_simics(vdev) || ivpu_is_fpga(vdev)) { 112 vdev->timeout.boot = 100000; 113 vdev->timeout.jsm = 50000; 114 vdev->timeout.tdr = 2000000; 115 vdev->timeout.reschedule_suspend = 1000; 116 } else { 117 vdev->timeout.boot = 1000; 118 vdev->timeout.jsm = 500; 119 vdev->timeout.tdr = 2000; 120 vdev->timeout.reschedule_suspend = 10; 121 } 122 } 123 124 static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev) 125 { 126 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US); 127 } 128 129 /* Send KMD initiated workpoint change */ 130 static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16 min_ratio, u16 max_ratio, 131 u16 target_ratio, u16 config) 132 { 133 int ret; 134 u32 val; 135 136 ret = ivpu_pll_wait_for_cmd_send(vdev); 137 if (ret) { 138 ivpu_err(vdev, "Failed to sync before WP request: %d\n", ret); 139 return ret; 140 } 141 142 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); 143 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); 144 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); 145 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val); 146 147 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); 148 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); 149 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val); 150 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val); 151 152 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2); 153 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, CONFIG, config, val); 154 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2, val); 155 156 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_CMD); 157 val = REG_SET_FLD(VPU_37XX_BUTTRESS_WP_REQ_CMD, SEND, val); 158 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_CMD, val); 159 160 ret = ivpu_pll_wait_for_cmd_send(vdev); 161 if (ret) 162 ivpu_err(vdev, "Failed to sync after WP request: %d\n", ret); 163 164 return ret; 165 } 166 167 static int ivpu_pll_wait_for_lock(struct ivpu_device *vdev, bool enable) 168 { 169 u32 exp_val = enable ? 0x1 : 0x0; 170 171 if (IVPU_WA(punit_disabled)) 172 return 0; 173 174 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_PLL_STATUS, LOCK, exp_val, PLL_TIMEOUT_US); 175 } 176 177 static int ivpu_pll_wait_for_status_ready(struct ivpu_device *vdev) 178 { 179 if (IVPU_WA(punit_disabled)) 180 return 0; 181 182 return REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, 1, PLL_TIMEOUT_US); 183 } 184 185 static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) 186 { 187 struct ivpu_hw_info *hw = vdev->hw; 188 u8 fuse_min_ratio, fuse_max_ratio, fuse_pn_ratio; 189 u32 fmin_fuse, fmax_fuse; 190 191 fmin_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMIN_FUSE); 192 fuse_min_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, MIN_RATIO, fmin_fuse); 193 fuse_pn_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMIN_FUSE, PN_RATIO, fmin_fuse); 194 195 fmax_fuse = REGB_RD32(VPU_37XX_BUTTRESS_FMAX_FUSE); 196 fuse_max_ratio = REG_GET_FLD(VPU_37XX_BUTTRESS_FMAX_FUSE, MAX_RATIO, fmax_fuse); 197 198 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio); 199 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio); 200 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); 201 } 202 203 static int ivpu_hw_37xx_wait_for_vpuip_bar(struct ivpu_device *vdev) 204 { 205 return REGV_POLL_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, AON, 0, 100); 206 } 207 208 static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) 209 { 210 struct ivpu_hw_info *hw = vdev->hw; 211 u16 target_ratio; 212 u16 config; 213 int ret; 214 215 if (IVPU_WA(punit_disabled)) { 216 ivpu_dbg(vdev, PM, "Skipping PLL request on %s\n", 217 ivpu_platform_to_str(vdev->platform)); 218 return 0; 219 } 220 221 if (enable) { 222 target_ratio = hw->pll.pn_ratio; 223 config = hw->config; 224 } else { 225 target_ratio = 0; 226 config = 0; 227 } 228 229 ivpu_dbg(vdev, PM, "PLL workpoint request: config 0x%04x pll ratio 0x%x\n", 230 config, target_ratio); 231 232 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, target_ratio, config); 233 if (ret) { 234 ivpu_err(vdev, "Failed to send PLL workpoint request: %d\n", ret); 235 return ret; 236 } 237 238 ret = ivpu_pll_wait_for_lock(vdev, enable); 239 if (ret) { 240 ivpu_err(vdev, "Timed out waiting for PLL lock\n"); 241 return ret; 242 } 243 244 if (enable) { 245 ret = ivpu_pll_wait_for_status_ready(vdev); 246 if (ret) { 247 ivpu_err(vdev, "Timed out waiting for PLL ready status\n"); 248 return ret; 249 } 250 251 ret = ivpu_hw_37xx_wait_for_vpuip_bar(vdev); 252 if (ret) { 253 ivpu_err(vdev, "Timed out waiting for VPUIP bar\n"); 254 return ret; 255 } 256 } 257 258 return 0; 259 } 260 261 static int ivpu_pll_enable(struct ivpu_device *vdev) 262 { 263 return ivpu_pll_drive(vdev, true); 264 } 265 266 static int ivpu_pll_disable(struct ivpu_device *vdev) 267 { 268 return ivpu_pll_drive(vdev, false); 269 } 270 271 static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev) 272 { 273 u32 val = 0; 274 275 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); 276 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); 277 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); 278 279 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); 280 } 281 282 static void ivpu_boot_host_ss_rst_drive(struct ivpu_device *vdev, bool enable) 283 { 284 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); 285 286 if (enable) { 287 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); 288 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); 289 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); 290 } else { 291 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); 292 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); 293 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); 294 } 295 296 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); 297 } 298 299 static void ivpu_boot_host_ss_clk_drive(struct ivpu_device *vdev, bool enable) 300 { 301 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); 302 303 if (enable) { 304 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); 305 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); 306 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); 307 } else { 308 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); 309 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); 310 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); 311 } 312 313 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); 314 } 315 316 static int ivpu_boot_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) 317 { 318 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); 319 320 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) 321 return -EIO; 322 323 return 0; 324 } 325 326 static int ivpu_boot_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) 327 { 328 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); 329 330 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) 331 return -EIO; 332 333 return 0; 334 } 335 336 static int ivpu_boot_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) 337 { 338 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); 339 340 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) 341 return -EIO; 342 343 return 0; 344 } 345 346 static int ivpu_boot_top_noc_qrenqn_check(struct ivpu_device *vdev, u32 exp_val) 347 { 348 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); 349 350 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || 351 !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) 352 return -EIO; 353 354 return 0; 355 } 356 357 static int ivpu_boot_top_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) 358 { 359 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QACCEPTN); 360 361 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || 362 !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) 363 return -EIO; 364 365 return 0; 366 } 367 368 static int ivpu_boot_top_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) 369 { 370 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QDENY); 371 372 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || 373 !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) 374 return -EIO; 375 376 return 0; 377 } 378 379 static int ivpu_boot_host_ss_configure(struct ivpu_device *vdev) 380 { 381 ivpu_boot_host_ss_rst_clr_assert(vdev); 382 383 return ivpu_boot_noc_qreqn_check(vdev, 0x0); 384 } 385 386 static void ivpu_boot_vpu_idle_gen_disable(struct ivpu_device *vdev) 387 { 388 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, 0x0); 389 } 390 391 static int ivpu_boot_host_ss_axi_drive(struct ivpu_device *vdev, bool enable) 392 { 393 int ret; 394 u32 val; 395 396 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); 397 if (enable) 398 val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); 399 else 400 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); 401 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); 402 403 ret = ivpu_boot_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); 404 if (ret) { 405 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); 406 return ret; 407 } 408 409 ret = ivpu_boot_noc_qdeny_check(vdev, 0x0); 410 if (ret) 411 ivpu_err(vdev, "Failed qdeny check: %d\n", ret); 412 413 return ret; 414 } 415 416 static int ivpu_boot_host_ss_axi_enable(struct ivpu_device *vdev) 417 { 418 return ivpu_boot_host_ss_axi_drive(vdev, true); 419 } 420 421 static int ivpu_boot_host_ss_top_noc_drive(struct ivpu_device *vdev, bool enable) 422 { 423 int ret; 424 u32 val; 425 426 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); 427 if (enable) { 428 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); 429 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); 430 } else { 431 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); 432 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); 433 } 434 REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val); 435 436 ret = ivpu_boot_top_noc_qacceptn_check(vdev, enable ? 0x1 : 0x0); 437 if (ret) { 438 ivpu_err(vdev, "Failed qacceptn check: %d\n", ret); 439 return ret; 440 } 441 442 ret = ivpu_boot_top_noc_qdeny_check(vdev, 0x0); 443 if (ret) 444 ivpu_err(vdev, "Failed qdeny check: %d\n", ret); 445 446 return ret; 447 } 448 449 static int ivpu_boot_host_ss_top_noc_enable(struct ivpu_device *vdev) 450 { 451 return ivpu_boot_host_ss_top_noc_drive(vdev, true); 452 } 453 454 static void ivpu_boot_pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) 455 { 456 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); 457 458 if (enable) 459 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); 460 else 461 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); 462 463 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); 464 } 465 466 static void ivpu_boot_pwr_island_drive(struct ivpu_device *vdev, bool enable) 467 { 468 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); 469 470 if (enable) 471 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); 472 else 473 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); 474 475 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); 476 } 477 478 static int ivpu_boot_wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) 479 { 480 /* FPGA model (UPF) is not power aware, skipped Power Island polling */ 481 if (ivpu_is_fpga(vdev)) 482 return 0; 483 484 return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, 485 exp_val, PWR_ISLAND_STATUS_TIMEOUT_US); 486 } 487 488 static void ivpu_boot_pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) 489 { 490 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); 491 492 if (enable) 493 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); 494 else 495 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); 496 497 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); 498 } 499 500 static void ivpu_boot_dpu_active_drive(struct ivpu_device *vdev, bool enable) 501 { 502 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); 503 504 if (enable) 505 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); 506 else 507 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); 508 509 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); 510 } 511 512 static int ivpu_boot_pwr_domain_enable(struct ivpu_device *vdev) 513 { 514 int ret; 515 516 ivpu_boot_pwr_island_trickle_drive(vdev, true); 517 ivpu_boot_pwr_island_drive(vdev, true); 518 519 ret = ivpu_boot_wait_for_pwr_island_status(vdev, 0x1); 520 if (ret) { 521 ivpu_err(vdev, "Timed out waiting for power island status\n"); 522 return ret; 523 } 524 525 ret = ivpu_boot_top_noc_qrenqn_check(vdev, 0x0); 526 if (ret) { 527 ivpu_err(vdev, "Failed qrenqn check %d\n", ret); 528 return ret; 529 } 530 531 ivpu_boot_host_ss_clk_drive(vdev, true); 532 ivpu_boot_pwr_island_isolation_drive(vdev, false); 533 ivpu_boot_host_ss_rst_drive(vdev, true); 534 ivpu_boot_dpu_active_drive(vdev, true); 535 536 return ret; 537 } 538 539 static void ivpu_boot_no_snoop_enable(struct ivpu_device *vdev) 540 { 541 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); 542 543 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); 544 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); 545 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); 546 547 REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); 548 } 549 550 static void ivpu_boot_tbu_mmu_enable(struct ivpu_device *vdev) 551 { 552 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); 553 554 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); 555 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); 556 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); 557 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); 558 559 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); 560 } 561 562 static void ivpu_boot_soc_cpu_boot(struct ivpu_device *vdev) 563 { 564 u32 val; 565 566 val = REGV_RD32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC); 567 val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); 568 569 val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); 570 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); 571 572 val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); 573 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); 574 575 val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); 576 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); 577 578 val = vdev->fw->entry_point >> 9; 579 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); 580 581 val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); 582 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); 583 584 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", 585 vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); 586 } 587 588 static int ivpu_boot_d0i3_drive(struct ivpu_device *vdev, bool enable) 589 { 590 int ret; 591 u32 val; 592 593 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); 594 if (ret) { 595 ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret); 596 return ret; 597 } 598 599 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL); 600 if (enable) 601 val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val); 602 else 603 val = REG_CLR_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, I3, val); 604 REGB_WR32(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, val); 605 606 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_D0I3_CONTROL, INPROGRESS, 0, TIMEOUT_US); 607 if (ret) 608 ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret); 609 610 return ret; 611 } 612 613 static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev) 614 { 615 struct ivpu_hw_info *hw = vdev->hw; 616 617 hw->tile_fuse = TILE_FUSE_ENABLE_BOTH; 618 hw->sku = TILE_SKU_BOTH_MTL; 619 hw->config = WP_CONFIG_2_TILE_4_3_RATIO; 620 621 ivpu_pll_init_frequency_ratios(vdev); 622 623 ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M); 624 ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M); 625 ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G); 626 ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G); 627 628 return 0; 629 } 630 631 static int ivpu_hw_37xx_reset(struct ivpu_device *vdev) 632 { 633 int ret; 634 u32 val; 635 636 if (IVPU_WA(punit_disabled)) 637 return 0; 638 639 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); 640 if (ret) { 641 ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n"); 642 return ret; 643 } 644 645 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_IP_RESET); 646 val = REG_SET_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, val); 647 REGB_WR32(VPU_37XX_BUTTRESS_VPU_IP_RESET, val); 648 649 ret = REGB_POLL_FLD(VPU_37XX_BUTTRESS_VPU_IP_RESET, TRIGGER, 0, TIMEOUT_US); 650 if (ret) 651 ivpu_err(vdev, "Timed out waiting for RESET completion\n"); 652 653 return ret; 654 } 655 656 static int ivpu_hw_37xx_d0i3_enable(struct ivpu_device *vdev) 657 { 658 int ret; 659 660 ret = ivpu_boot_d0i3_drive(vdev, true); 661 if (ret) 662 ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret); 663 664 udelay(5); /* VPU requires 5 us to complete the transition */ 665 666 return ret; 667 } 668 669 static int ivpu_hw_37xx_d0i3_disable(struct ivpu_device *vdev) 670 { 671 int ret; 672 673 ret = ivpu_boot_d0i3_drive(vdev, false); 674 if (ret) 675 ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret); 676 677 return ret; 678 } 679 680 static int ivpu_hw_37xx_power_up(struct ivpu_device *vdev) 681 { 682 int ret; 683 684 ivpu_hw_read_platform(vdev); 685 ivpu_hw_wa_init(vdev); 686 ivpu_hw_timeouts_init(vdev); 687 688 ret = ivpu_hw_37xx_reset(vdev); 689 if (ret) 690 ivpu_warn(vdev, "Failed to reset HW: %d\n", ret); 691 692 ret = ivpu_hw_37xx_d0i3_disable(vdev); 693 if (ret) 694 ivpu_warn(vdev, "Failed to disable D0I3: %d\n", ret); 695 696 ret = ivpu_pll_enable(vdev); 697 if (ret) { 698 ivpu_err(vdev, "Failed to enable PLL: %d\n", ret); 699 return ret; 700 } 701 702 ret = ivpu_boot_host_ss_configure(vdev); 703 if (ret) { 704 ivpu_err(vdev, "Failed to configure host SS: %d\n", ret); 705 return ret; 706 } 707 708 /* 709 * The control circuitry for vpu_idle indication logic powers up active. 710 * To ensure unnecessary low power mode signal from LRT during bring up, 711 * KMD disables the circuitry prior to bringing up the Main Power island. 712 */ 713 ivpu_boot_vpu_idle_gen_disable(vdev); 714 715 ret = ivpu_boot_pwr_domain_enable(vdev); 716 if (ret) { 717 ivpu_err(vdev, "Failed to enable power domain: %d\n", ret); 718 return ret; 719 } 720 721 ret = ivpu_boot_host_ss_axi_enable(vdev); 722 if (ret) { 723 ivpu_err(vdev, "Failed to enable AXI: %d\n", ret); 724 return ret; 725 } 726 727 ret = ivpu_boot_host_ss_top_noc_enable(vdev); 728 if (ret) 729 ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret); 730 731 return ret; 732 } 733 734 static int ivpu_hw_37xx_boot_fw(struct ivpu_device *vdev) 735 { 736 ivpu_boot_no_snoop_enable(vdev); 737 ivpu_boot_tbu_mmu_enable(vdev); 738 ivpu_boot_soc_cpu_boot(vdev); 739 740 return 0; 741 } 742 743 static bool ivpu_hw_37xx_is_idle(struct ivpu_device *vdev) 744 { 745 u32 val; 746 747 if (IVPU_WA(punit_disabled)) 748 return true; 749 750 val = REGB_RD32(VPU_37XX_BUTTRESS_VPU_STATUS); 751 return REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, READY, val) && 752 REG_TEST_FLD(VPU_37XX_BUTTRESS_VPU_STATUS, IDLE, val); 753 } 754 755 static int ivpu_hw_37xx_power_down(struct ivpu_device *vdev) 756 { 757 int ret = 0; 758 759 if (!ivpu_hw_37xx_is_idle(vdev) && ivpu_hw_37xx_reset(vdev)) 760 ivpu_err(vdev, "Failed to reset the VPU\n"); 761 762 if (ivpu_pll_disable(vdev)) { 763 ivpu_err(vdev, "Failed to disable PLL\n"); 764 ret = -EIO; 765 } 766 767 if (ivpu_hw_37xx_d0i3_enable(vdev)) { 768 ivpu_err(vdev, "Failed to enter D0I3\n"); 769 ret = -EIO; 770 } 771 772 return ret; 773 } 774 775 static void ivpu_hw_37xx_wdt_disable(struct ivpu_device *vdev) 776 { 777 u32 val; 778 779 /* Enable writing and set non-zero WDT value */ 780 REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); 781 REGV_WR32(MTL_VPU_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); 782 783 /* Enable writing and disable watchdog timer */ 784 REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); 785 REGV_WR32(MTL_VPU_CPU_SS_TIM_WDOG_EN, 0); 786 787 /* Now clear the timeout interrupt */ 788 val = REGV_RD32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG); 789 val = REG_CLR_FLD(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); 790 REGV_WR32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, val); 791 } 792 793 static u32 ivpu_hw_37xx_pll_to_freq(u32 ratio, u32 config) 794 { 795 u32 pll_clock = PLL_REF_CLK_FREQ * ratio; 796 u32 cpu_clock; 797 798 if ((config & 0xff) == PLL_RATIO_4_3) 799 cpu_clock = pll_clock * 2 / 4; 800 else 801 cpu_clock = pll_clock * 2 / 5; 802 803 return cpu_clock; 804 } 805 806 /* Register indirect accesses */ 807 static u32 ivpu_hw_37xx_reg_pll_freq_get(struct ivpu_device *vdev) 808 { 809 u32 pll_curr_ratio; 810 811 pll_curr_ratio = REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL); 812 pll_curr_ratio &= VPU_37XX_BUTTRESS_CURRENT_PLL_RATIO_MASK; 813 814 if (!ivpu_is_silicon(vdev)) 815 return PLL_SIMULATION_FREQ; 816 817 return ivpu_hw_37xx_pll_to_freq(pll_curr_ratio, vdev->hw->config); 818 } 819 820 static u32 ivpu_hw_37xx_reg_telemetry_offset_get(struct ivpu_device *vdev) 821 { 822 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_OFFSET); 823 } 824 825 static u32 ivpu_hw_37xx_reg_telemetry_size_get(struct ivpu_device *vdev) 826 { 827 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_SIZE); 828 } 829 830 static u32 ivpu_hw_37xx_reg_telemetry_enable_get(struct ivpu_device *vdev) 831 { 832 return REGB_RD32(VPU_37XX_BUTTRESS_VPU_TELEMETRY_ENABLE); 833 } 834 835 static void ivpu_hw_37xx_reg_db_set(struct ivpu_device *vdev, u32 db_id) 836 { 837 u32 reg_stride = MTL_VPU_CPU_SS_DOORBELL_1 - MTL_VPU_CPU_SS_DOORBELL_0; 838 u32 val = REG_FLD(MTL_VPU_CPU_SS_DOORBELL_0, SET); 839 840 REGV_WR32I(MTL_VPU_CPU_SS_DOORBELL_0, reg_stride, db_id, val); 841 } 842 843 static u32 ivpu_hw_37xx_reg_ipc_rx_addr_get(struct ivpu_device *vdev) 844 { 845 return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM); 846 } 847 848 static u32 ivpu_hw_37xx_reg_ipc_rx_count_get(struct ivpu_device *vdev) 849 { 850 u32 count = REGV_RD32_SILENT(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT); 851 852 return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); 853 } 854 855 static void ivpu_hw_37xx_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) 856 { 857 REGV_WR32(MTL_VPU_CPU_SS_TIM_IPC_FIFO, vpu_addr); 858 } 859 860 static void ivpu_hw_37xx_irq_clear(struct ivpu_device *vdev) 861 { 862 REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); 863 } 864 865 static void ivpu_hw_37xx_irq_enable(struct ivpu_device *vdev) 866 { 867 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); 868 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); 869 REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK); 870 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); 871 } 872 873 static void ivpu_hw_37xx_irq_disable(struct ivpu_device *vdev) 874 { 875 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); 876 REGB_WR32(VPU_37XX_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK); 877 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); 878 REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); 879 } 880 881 static void ivpu_hw_37xx_irq_wdt_nce_handler(struct ivpu_device *vdev) 882 { 883 ivpu_err_ratelimited(vdev, "WDT NCE irq\n"); 884 885 ivpu_pm_schedule_recovery(vdev); 886 } 887 888 static void ivpu_hw_37xx_irq_wdt_mss_handler(struct ivpu_device *vdev) 889 { 890 ivpu_err_ratelimited(vdev, "WDT MSS irq\n"); 891 892 ivpu_hw_wdt_disable(vdev); 893 ivpu_pm_schedule_recovery(vdev); 894 } 895 896 static void ivpu_hw_37xx_irq_noc_firewall_handler(struct ivpu_device *vdev) 897 { 898 ivpu_err_ratelimited(vdev, "NOC Firewall irq\n"); 899 900 ivpu_pm_schedule_recovery(vdev); 901 } 902 903 /* Handler for IRQs from VPU core (irqV) */ 904 static u32 ivpu_hw_37xx_irqv_handler(struct ivpu_device *vdev, int irq) 905 { 906 u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; 907 908 REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status); 909 910 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) 911 ivpu_mmu_irq_evtq_handler(vdev); 912 913 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) 914 ivpu_ipc_irq_handler(vdev); 915 916 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) 917 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); 918 919 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) 920 ivpu_mmu_irq_gerr_handler(vdev); 921 922 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) 923 ivpu_hw_37xx_irq_wdt_mss_handler(vdev); 924 925 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) 926 ivpu_hw_37xx_irq_wdt_nce_handler(vdev); 927 928 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) 929 ivpu_hw_37xx_irq_noc_firewall_handler(vdev); 930 931 return status; 932 } 933 934 /* Handler for IRQs from Buttress core (irqB) */ 935 static u32 ivpu_hw_37xx_irqb_handler(struct ivpu_device *vdev, int irq) 936 { 937 u32 status = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; 938 bool schedule_recovery = false; 939 940 if (status == 0) 941 return 0; 942 943 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status)) 944 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", 945 REGB_RD32(VPU_37XX_BUTTRESS_CURRENT_PLL)); 946 947 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, status)) { 948 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); 949 REGB_WR32(VPU_37XX_BUTTRESS_ATS_ERR_CLEAR, 0x1); 950 schedule_recovery = true; 951 } 952 953 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, status)) { 954 u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG); 955 956 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", 957 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log), 958 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log), 959 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log)); 960 REGB_WR32(VPU_37XX_BUTTRESS_UFI_ERR_CLEAR, 0x1); 961 schedule_recovery = true; 962 } 963 964 /* This must be done after interrupts are cleared at the source. */ 965 if (IVPU_WA(interrupt_clear_with_0)) 966 /* 967 * Writing 1 triggers an interrupt, so we can't perform read update write. 968 * Clear local interrupt status by writing 0 to all bits. 969 */ 970 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0); 971 else 972 REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, status); 973 974 if (schedule_recovery) 975 ivpu_pm_schedule_recovery(vdev); 976 977 return status; 978 } 979 980 static irqreturn_t ivpu_hw_37xx_irq_handler(int irq, void *ptr) 981 { 982 struct ivpu_device *vdev = ptr; 983 u32 ret_irqv, ret_irqb; 984 985 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x1); 986 987 ret_irqv = ivpu_hw_37xx_irqv_handler(vdev, irq); 988 ret_irqb = ivpu_hw_37xx_irqb_handler(vdev, irq); 989 990 /* Re-enable global interrupts to re-trigger MSI for pending interrupts */ 991 REGB_WR32(VPU_37XX_BUTTRESS_GLOBAL_INT_MASK, 0x0); 992 993 return IRQ_RETVAL(ret_irqb | ret_irqv); 994 } 995 996 static void ivpu_hw_37xx_diagnose_failure(struct ivpu_device *vdev) 997 { 998 u32 irqv = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; 999 u32 irqb = REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; 1000 1001 if (ivpu_hw_37xx_reg_ipc_rx_count_get(vdev)) 1002 ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); 1003 1004 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, irqv)) 1005 ivpu_err(vdev, "WDT MSS timeout detected\n"); 1006 1007 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, irqv)) 1008 ivpu_err(vdev, "WDT NCE timeout detected\n"); 1009 1010 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, irqv)) 1011 ivpu_err(vdev, "NOC Firewall irq detected\n"); 1012 1013 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR, irqb)) 1014 ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_37XX_BUTTRESS_ATS_ERR_LOG_0)); 1015 1016 if (REG_TEST_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR, irqb)) { 1017 u32 ufi_log = REGB_RD32(VPU_37XX_BUTTRESS_UFI_ERR_LOG); 1018 1019 ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx", 1020 ufi_log, REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, OPCODE, ufi_log), 1021 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, AXI_ID, ufi_log), 1022 REG_GET_FLD(VPU_37XX_BUTTRESS_UFI_ERR_LOG, CQ_ID, ufi_log)); 1023 } 1024 } 1025 1026 const struct ivpu_hw_ops ivpu_hw_37xx_ops = { 1027 .info_init = ivpu_hw_37xx_info_init, 1028 .power_up = ivpu_hw_37xx_power_up, 1029 .is_idle = ivpu_hw_37xx_is_idle, 1030 .power_down = ivpu_hw_37xx_power_down, 1031 .reset = ivpu_hw_37xx_reset, 1032 .boot_fw = ivpu_hw_37xx_boot_fw, 1033 .wdt_disable = ivpu_hw_37xx_wdt_disable, 1034 .diagnose_failure = ivpu_hw_37xx_diagnose_failure, 1035 .reg_pll_freq_get = ivpu_hw_37xx_reg_pll_freq_get, 1036 .reg_telemetry_offset_get = ivpu_hw_37xx_reg_telemetry_offset_get, 1037 .reg_telemetry_size_get = ivpu_hw_37xx_reg_telemetry_size_get, 1038 .reg_telemetry_enable_get = ivpu_hw_37xx_reg_telemetry_enable_get, 1039 .reg_db_set = ivpu_hw_37xx_reg_db_set, 1040 .reg_ipc_rx_addr_get = ivpu_hw_37xx_reg_ipc_rx_addr_get, 1041 .reg_ipc_rx_count_get = ivpu_hw_37xx_reg_ipc_rx_count_get, 1042 .reg_ipc_tx_set = ivpu_hw_37xx_reg_ipc_tx_set, 1043 .irq_clear = ivpu_hw_37xx_irq_clear, 1044 .irq_enable = ivpu_hw_37xx_irq_enable, 1045 .irq_disable = ivpu_hw_37xx_irq_disable, 1046 .irq_handler = ivpu_hw_37xx_irq_handler, 1047 }; 1048