1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 24 #define FW_RUNTIME_MAX_SIZE SZ_512M 25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 28 #define FW_VERSION_HEADER_SIZE SZ_4K 29 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 30 31 #define WATCHDOG_MSS_REDIRECT 32 32 #define WATCHDOG_NCE_REDIRECT 33 33 34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 35 36 #define IVPU_FW_CHECK_API(vdev, fw_hdr, name, min_major) \ 37 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 38 VPU_##name##_API_VER_INDEX, \ 39 VPU_##name##_API_VER_MAJOR, \ 40 VPU_##name##_API_VER_MINOR, min_major) 41 42 static char *ivpu_firmware; 43 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 44 MODULE_PARM_DESC(firmware, "VPU firmware binary in /lib/firmware/.."); 45 46 /* TODO: Remove mtl_vpu.bin from names after transition to generation based FW names */ 47 static struct { 48 int gen; 49 const char *name; 50 } fw_names[] = { 51 { IVPU_HW_37XX, "vpu_37xx.bin" }, 52 { IVPU_HW_37XX, "mtl_vpu.bin" }, 53 { IVPU_HW_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, 54 { IVPU_HW_40XX, "vpu_40xx.bin" }, 55 { IVPU_HW_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, 56 }; 57 58 /* Production fw_names from the table above */ 59 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin"); 60 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin"); 61 62 static int ivpu_fw_request(struct ivpu_device *vdev) 63 { 64 int ret = -ENOENT; 65 int i; 66 67 if (ivpu_firmware) { 68 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 69 if (!ret) 70 vdev->fw->name = ivpu_firmware; 71 return ret; 72 } 73 74 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 75 if (fw_names[i].gen != ivpu_hw_gen(vdev)) 76 continue; 77 78 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); 79 if (!ret) { 80 vdev->fw->name = fw_names[i].name; 81 return 0; 82 } 83 } 84 85 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 86 return ret; 87 } 88 89 static int 90 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 91 const char *str, int index, u16 expected_major, u16 expected_minor, 92 u16 min_major) 93 { 94 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 95 u16 minor = (u16)(fw_hdr->api_version[index]); 96 97 if (major < min_major) { 98 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 99 str, major, minor, min_major); 100 return -EINVAL; 101 } 102 if (major != expected_major) { 103 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 104 str, major, minor, expected_major, expected_minor); 105 } 106 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 107 str, major, minor, expected_major, expected_minor); 108 109 return 0; 110 } 111 112 static int ivpu_fw_parse(struct ivpu_device *vdev) 113 { 114 struct ivpu_fw_info *fw = vdev->fw; 115 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 116 u64 runtime_addr, image_load_addr, runtime_size, image_size; 117 118 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 119 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 120 return -EINVAL; 121 } 122 123 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 124 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 125 return -EINVAL; 126 } 127 128 runtime_addr = fw_hdr->boot_params_load_address; 129 runtime_size = fw_hdr->runtime_size; 130 image_load_addr = fw_hdr->image_load_address; 131 image_size = fw_hdr->image_size; 132 133 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 134 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 135 return -EINVAL; 136 } 137 138 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 139 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 140 return -EINVAL; 141 } 142 143 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 144 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 145 return -EINVAL; 146 } 147 148 if (image_load_addr < runtime_addr || 149 image_load_addr + image_size > runtime_addr + runtime_size) { 150 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 151 image_load_addr, image_size); 152 return -EINVAL; 153 } 154 155 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 156 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 157 return -EINVAL; 158 } 159 160 if (fw_hdr->entry_point < image_load_addr || 161 fw_hdr->entry_point >= image_load_addr + image_size) { 162 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 163 return -EINVAL; 164 } 165 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 166 fw_hdr->header_version, fw_hdr->image_format); 167 168 ivpu_info(vdev, "Firmware: %s, version: %s", fw->name, 169 (const char *)fw_hdr + VPU_FW_HEADER_SIZE); 170 171 if (IVPU_FW_CHECK_API(vdev, fw_hdr, BOOT, 3)) 172 return -EINVAL; 173 if (IVPU_FW_CHECK_API(vdev, fw_hdr, JSM, 3)) 174 return -EINVAL; 175 176 fw->runtime_addr = runtime_addr; 177 fw->runtime_size = runtime_size; 178 fw->image_load_offset = image_load_addr - runtime_addr; 179 fw->image_size = image_size; 180 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 181 182 fw->cold_boot_entry_point = fw_hdr->entry_point; 183 fw->entry_point = fw->cold_boot_entry_point; 184 185 fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL); 186 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 187 fw->trace_hw_component_mask = -1; 188 189 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 190 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 191 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 192 fw->runtime_addr, image_load_addr, fw->entry_point); 193 194 return 0; 195 } 196 197 static void ivpu_fw_release(struct ivpu_device *vdev) 198 { 199 release_firmware(vdev->fw->file); 200 } 201 202 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 203 { 204 struct ivpu_fw_info *fw = vdev->fw; 205 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 206 u64 size = FW_SHARED_MEM_SIZE; 207 208 if (start + size > FW_GLOBAL_MEM_END) { 209 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 210 return -EINVAL; 211 } 212 213 ivpu_hw_init_range(&vdev->hw->ranges.global, start, size); 214 return 0; 215 } 216 217 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 218 { 219 struct ivpu_fw_info *fw = vdev->fw; 220 int log_verb_size; 221 int ret; 222 223 ret = ivpu_fw_update_global_range(vdev); 224 if (ret) 225 return ret; 226 227 fw->mem = ivpu_bo_alloc_internal(vdev, fw->runtime_addr, fw->runtime_size, DRM_IVPU_BO_WC); 228 if (!fw->mem) { 229 ivpu_err(vdev, "Failed to allocate firmware runtime memory\n"); 230 return -ENOMEM; 231 } 232 233 fw->mem_log_crit = ivpu_bo_alloc_internal(vdev, 0, IVPU_FW_CRITICAL_BUFFER_SIZE, 234 DRM_IVPU_BO_CACHED); 235 if (!fw->mem_log_crit) { 236 ivpu_err(vdev, "Failed to allocate critical log buffer\n"); 237 ret = -ENOMEM; 238 goto err_free_fw_mem; 239 } 240 241 if (ivpu_log_level <= IVPU_FW_LOG_INFO) 242 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 243 else 244 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 245 246 fw->mem_log_verb = ivpu_bo_alloc_internal(vdev, 0, log_verb_size, DRM_IVPU_BO_CACHED); 247 if (!fw->mem_log_verb) { 248 ivpu_err(vdev, "Failed to allocate verbose log buffer\n"); 249 ret = -ENOMEM; 250 goto err_free_log_crit; 251 } 252 253 if (fw->shave_nn_size) { 254 fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.shave.start, 255 fw->shave_nn_size, DRM_IVPU_BO_UNCACHED); 256 if (!fw->mem_shave_nn) { 257 ivpu_err(vdev, "Failed to allocate shavenn buffer\n"); 258 ret = -ENOMEM; 259 goto err_free_log_verb; 260 } 261 } 262 263 return 0; 264 265 err_free_log_verb: 266 ivpu_bo_free_internal(fw->mem_log_verb); 267 err_free_log_crit: 268 ivpu_bo_free_internal(fw->mem_log_crit); 269 err_free_fw_mem: 270 ivpu_bo_free_internal(fw->mem); 271 return ret; 272 } 273 274 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 275 { 276 struct ivpu_fw_info *fw = vdev->fw; 277 278 if (fw->mem_shave_nn) { 279 ivpu_bo_free_internal(fw->mem_shave_nn); 280 fw->mem_shave_nn = NULL; 281 } 282 283 ivpu_bo_free_internal(fw->mem_log_verb); 284 ivpu_bo_free_internal(fw->mem_log_crit); 285 ivpu_bo_free_internal(fw->mem); 286 287 fw->mem_log_verb = NULL; 288 fw->mem_log_crit = NULL; 289 fw->mem = NULL; 290 } 291 292 int ivpu_fw_init(struct ivpu_device *vdev) 293 { 294 int ret; 295 296 ret = ivpu_fw_request(vdev); 297 if (ret) 298 return ret; 299 300 ret = ivpu_fw_parse(vdev); 301 if (ret) 302 goto err_fw_release; 303 304 ret = ivpu_fw_mem_init(vdev); 305 if (ret) 306 goto err_fw_release; 307 308 return 0; 309 310 err_fw_release: 311 ivpu_fw_release(vdev); 312 return ret; 313 } 314 315 void ivpu_fw_fini(struct ivpu_device *vdev) 316 { 317 ivpu_fw_mem_fini(vdev); 318 ivpu_fw_release(vdev); 319 } 320 321 int ivpu_fw_load(struct ivpu_device *vdev) 322 { 323 struct ivpu_fw_info *fw = vdev->fw; 324 u64 image_end_offset = fw->image_load_offset + fw->image_size; 325 326 memset(fw->mem->kvaddr, 0, fw->image_load_offset); 327 memcpy(fw->mem->kvaddr + fw->image_load_offset, 328 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 329 330 if (IVPU_WA(clear_runtime_mem)) { 331 u8 *start = fw->mem->kvaddr + image_end_offset; 332 u64 size = fw->mem->base.size - image_end_offset; 333 334 memset(start, 0, size); 335 } 336 337 wmb(); /* Flush WC buffers after writing fw->mem */ 338 339 return 0; 340 } 341 342 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 343 { 344 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 345 boot_params->magic); 346 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 347 boot_params->vpu_id); 348 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 349 boot_params->vpu_count); 350 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 351 boot_params->frequency); 352 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 353 boot_params->perf_clk_frequency); 354 355 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 356 boot_params->ipc_header_area_start); 357 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 358 boot_params->ipc_header_area_size); 359 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 360 boot_params->shared_region_base); 361 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 362 boot_params->shared_region_size); 363 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 364 boot_params->ipc_payload_area_start); 365 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 366 boot_params->ipc_payload_area_size); 367 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 368 boot_params->global_aliased_pio_base); 369 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 370 boot_params->global_aliased_pio_size); 371 372 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 373 boot_params->autoconfig); 374 375 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 376 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 377 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 378 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 379 380 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 381 boot_params->global_memory_allocator_base); 382 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 383 boot_params->global_memory_allocator_size); 384 385 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 386 boot_params->shave_nn_fw_base); 387 388 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 389 boot_params->watchdog_irq_mss); 390 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 391 boot_params->watchdog_irq_nce); 392 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 393 boot_params->host_to_vpu_irq); 394 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 395 boot_params->job_done_irq); 396 397 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 398 boot_params->host_version_id); 399 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 400 boot_params->si_stepping); 401 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 402 boot_params->device_id); 403 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 404 boot_params->feature_exclusion); 405 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 406 boot_params->sku); 407 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 408 boot_params->min_freq_pll_ratio); 409 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 410 boot_params->pn_freq_pll_ratio); 411 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 412 boot_params->max_freq_pll_ratio); 413 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 414 boot_params->default_trace_level); 415 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 416 boot_params->tracing_buff_message_format_mask); 417 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 418 boot_params->trace_destination_mask); 419 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 420 boot_params->trace_hw_component_mask); 421 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 422 boot_params->boot_type); 423 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 424 boot_params->punit_telemetry_sram_base); 425 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 426 boot_params->punit_telemetry_sram_size); 427 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 428 boot_params->vpu_telemetry_enable); 429 } 430 431 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 432 { 433 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 434 435 /* In case of warm boot we only have to reset the entrypoint addr */ 436 if (!ivpu_fw_is_cold_boot(vdev)) { 437 boot_params->save_restore_ret_address = 0; 438 vdev->pm->is_warmboot = true; 439 wmb(); /* Flush WC buffers after writing save_restore_ret_address */ 440 return; 441 } 442 443 vdev->pm->is_warmboot = false; 444 445 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 446 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 447 boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev); 448 449 /* 450 * Uncached region of VPU address space, covers IPC buffers, job queues 451 * and log buffers, programmable to L2$ Uncached by VPU MTRR 452 */ 453 boot_params->shared_region_base = vdev->hw->ranges.global.start; 454 boot_params->shared_region_size = vdev->hw->ranges.global.end - 455 vdev->hw->ranges.global.start; 456 457 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 458 boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2; 459 460 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2; 461 boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2; 462 463 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start; 464 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user); 465 466 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 467 boot_params->autoconfig = 1; 468 469 /* Enable L2 cache for first 2GB of high memory */ 470 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 471 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 472 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start); 473 474 if (vdev->fw->mem_shave_nn) 475 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 476 477 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 478 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 479 boot_params->si_stepping = ivpu_revision(vdev); 480 boot_params->device_id = ivpu_device_id(vdev); 481 boot_params->feature_exclusion = vdev->hw->tile_fuse; 482 boot_params->sku = vdev->hw->sku; 483 484 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 485 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 486 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 487 488 boot_params->default_trace_level = vdev->fw->trace_level; 489 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 490 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 491 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 492 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 493 boot_params->crit_tracing_buff_size = vdev->fw->mem_log_crit->base.size; 494 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 495 boot_params->verbose_tracing_buff_size = vdev->fw->mem_log_verb->base.size; 496 497 boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev); 498 boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev); 499 boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev); 500 501 wmb(); /* Flush WC buffers after writing bootparams */ 502 503 ivpu_fw_boot_params_print(vdev, boot_params); 504 } 505