1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 24 #define FW_RUNTIME_MAX_SIZE SZ_512M 25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 28 #define FW_VERSION_HEADER_SIZE SZ_4K 29 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 30 31 #define WATCHDOG_MSS_REDIRECT 32 32 #define WATCHDOG_NCE_REDIRECT 33 33 34 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 35 36 #define IVPU_FW_CHECK_API(vdev, fw_hdr, name, min_major) \ 37 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 38 VPU_##name##_API_VER_INDEX, \ 39 VPU_##name##_API_VER_MAJOR, \ 40 VPU_##name##_API_VER_MINOR, min_major) 41 42 static char *ivpu_firmware; 43 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 44 MODULE_PARM_DESC(firmware, "VPU firmware binary in /lib/firmware/.."); 45 46 static int ivpu_fw_request(struct ivpu_device *vdev) 47 { 48 static const char * const fw_names[] = { 49 "mtl_vpu.bin", 50 "intel/vpu/mtl_vpu_v0.0.bin" 51 }; 52 int ret = -ENOENT; 53 int i; 54 55 if (ivpu_firmware) { 56 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 57 if (!ret) 58 vdev->fw->name = ivpu_firmware; 59 return ret; 60 } 61 62 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 63 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i], vdev->drm.dev); 64 if (!ret) { 65 vdev->fw->name = fw_names[i]; 66 return 0; 67 } 68 } 69 70 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 71 return ret; 72 } 73 74 static int 75 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 76 const char *str, int index, u16 expected_major, u16 expected_minor, 77 u16 min_major) 78 { 79 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 80 u16 minor = (u16)(fw_hdr->api_version[index]); 81 82 if (major < min_major) { 83 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 84 str, major, minor, min_major); 85 return -EINVAL; 86 } 87 if (major != expected_major) { 88 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 89 str, major, minor, expected_major, expected_minor); 90 } 91 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 92 str, major, minor, expected_major, expected_minor); 93 94 return 0; 95 } 96 97 static int ivpu_fw_parse(struct ivpu_device *vdev) 98 { 99 struct ivpu_fw_info *fw = vdev->fw; 100 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 101 u64 runtime_addr, image_load_addr, runtime_size, image_size; 102 103 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 104 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 105 return -EINVAL; 106 } 107 108 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 109 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 110 return -EINVAL; 111 } 112 113 runtime_addr = fw_hdr->boot_params_load_address; 114 runtime_size = fw_hdr->runtime_size; 115 image_load_addr = fw_hdr->image_load_address; 116 image_size = fw_hdr->image_size; 117 118 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 119 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 120 return -EINVAL; 121 } 122 123 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 124 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 125 return -EINVAL; 126 } 127 128 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 129 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 130 return -EINVAL; 131 } 132 133 if (image_load_addr < runtime_addr || 134 image_load_addr + image_size > runtime_addr + runtime_size) { 135 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 136 image_load_addr, image_size); 137 return -EINVAL; 138 } 139 140 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 141 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 142 return -EINVAL; 143 } 144 145 if (fw_hdr->entry_point < image_load_addr || 146 fw_hdr->entry_point >= image_load_addr + image_size) { 147 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 148 return -EINVAL; 149 } 150 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 151 fw_hdr->header_version, fw_hdr->image_format); 152 153 ivpu_info(vdev, "Firmware: %s, version: %s", fw->name, 154 (const char *)fw_hdr + VPU_FW_HEADER_SIZE); 155 156 if (IVPU_FW_CHECK_API(vdev, fw_hdr, BOOT, 3)) 157 return -EINVAL; 158 if (IVPU_FW_CHECK_API(vdev, fw_hdr, JSM, 3)) 159 return -EINVAL; 160 161 fw->runtime_addr = runtime_addr; 162 fw->runtime_size = runtime_size; 163 fw->image_load_offset = image_load_addr - runtime_addr; 164 fw->image_size = image_size; 165 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 166 167 fw->cold_boot_entry_point = fw_hdr->entry_point; 168 fw->entry_point = fw->cold_boot_entry_point; 169 170 fw->trace_level = min_t(u32, ivpu_log_level, IVPU_FW_LOG_FATAL); 171 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 172 fw->trace_hw_component_mask = -1; 173 174 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 175 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 176 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 177 fw->runtime_addr, image_load_addr, fw->entry_point); 178 179 return 0; 180 } 181 182 static void ivpu_fw_release(struct ivpu_device *vdev) 183 { 184 release_firmware(vdev->fw->file); 185 } 186 187 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 188 { 189 struct ivpu_fw_info *fw = vdev->fw; 190 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 191 u64 size = FW_SHARED_MEM_SIZE; 192 193 if (start + size > FW_GLOBAL_MEM_END) { 194 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 195 return -EINVAL; 196 } 197 198 ivpu_hw_init_range(&vdev->hw->ranges.global_low, start, size); 199 return 0; 200 } 201 202 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 203 { 204 struct ivpu_fw_info *fw = vdev->fw; 205 int log_verb_size; 206 int ret; 207 208 ret = ivpu_fw_update_global_range(vdev); 209 if (ret) 210 return ret; 211 212 fw->mem = ivpu_bo_alloc_internal(vdev, fw->runtime_addr, fw->runtime_size, DRM_IVPU_BO_WC); 213 if (!fw->mem) { 214 ivpu_err(vdev, "Failed to allocate firmware runtime memory\n"); 215 return -ENOMEM; 216 } 217 218 fw->mem_log_crit = ivpu_bo_alloc_internal(vdev, 0, IVPU_FW_CRITICAL_BUFFER_SIZE, 219 DRM_IVPU_BO_CACHED); 220 if (!fw->mem_log_crit) { 221 ivpu_err(vdev, "Failed to allocate critical log buffer\n"); 222 ret = -ENOMEM; 223 goto err_free_fw_mem; 224 } 225 226 if (ivpu_log_level <= IVPU_FW_LOG_INFO) 227 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 228 else 229 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 230 231 fw->mem_log_verb = ivpu_bo_alloc_internal(vdev, 0, log_verb_size, DRM_IVPU_BO_CACHED); 232 if (!fw->mem_log_verb) { 233 ivpu_err(vdev, "Failed to allocate verbose log buffer\n"); 234 ret = -ENOMEM; 235 goto err_free_log_crit; 236 } 237 238 if (fw->shave_nn_size) { 239 fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.global_high.start, 240 fw->shave_nn_size, DRM_IVPU_BO_UNCACHED); 241 if (!fw->mem_shave_nn) { 242 ivpu_err(vdev, "Failed to allocate shavenn buffer\n"); 243 ret = -ENOMEM; 244 goto err_free_log_verb; 245 } 246 } 247 248 return 0; 249 250 err_free_log_verb: 251 ivpu_bo_free_internal(fw->mem_log_verb); 252 err_free_log_crit: 253 ivpu_bo_free_internal(fw->mem_log_crit); 254 err_free_fw_mem: 255 ivpu_bo_free_internal(fw->mem); 256 return ret; 257 } 258 259 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 260 { 261 struct ivpu_fw_info *fw = vdev->fw; 262 263 if (fw->mem_shave_nn) { 264 ivpu_bo_free_internal(fw->mem_shave_nn); 265 fw->mem_shave_nn = NULL; 266 } 267 268 ivpu_bo_free_internal(fw->mem_log_verb); 269 ivpu_bo_free_internal(fw->mem_log_crit); 270 ivpu_bo_free_internal(fw->mem); 271 272 fw->mem_log_verb = NULL; 273 fw->mem_log_crit = NULL; 274 fw->mem = NULL; 275 } 276 277 int ivpu_fw_init(struct ivpu_device *vdev) 278 { 279 int ret; 280 281 ret = ivpu_fw_request(vdev); 282 if (ret) 283 return ret; 284 285 ret = ivpu_fw_parse(vdev); 286 if (ret) 287 goto err_fw_release; 288 289 ret = ivpu_fw_mem_init(vdev); 290 if (ret) 291 goto err_fw_release; 292 293 return 0; 294 295 err_fw_release: 296 ivpu_fw_release(vdev); 297 return ret; 298 } 299 300 void ivpu_fw_fini(struct ivpu_device *vdev) 301 { 302 ivpu_fw_mem_fini(vdev); 303 ivpu_fw_release(vdev); 304 } 305 306 int ivpu_fw_load(struct ivpu_device *vdev) 307 { 308 struct ivpu_fw_info *fw = vdev->fw; 309 u64 image_end_offset = fw->image_load_offset + fw->image_size; 310 311 memset(fw->mem->kvaddr, 0, fw->image_load_offset); 312 memcpy(fw->mem->kvaddr + fw->image_load_offset, 313 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 314 315 if (IVPU_WA(clear_runtime_mem)) { 316 u8 *start = fw->mem->kvaddr + image_end_offset; 317 u64 size = fw->mem->base.size - image_end_offset; 318 319 memset(start, 0, size); 320 } 321 322 wmb(); /* Flush WC buffers after writing fw->mem */ 323 324 return 0; 325 } 326 327 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 328 { 329 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 330 boot_params->magic); 331 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 332 boot_params->vpu_id); 333 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 334 boot_params->vpu_count); 335 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 336 boot_params->frequency); 337 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 338 boot_params->perf_clk_frequency); 339 340 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 341 boot_params->ipc_header_area_start); 342 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 343 boot_params->ipc_header_area_size); 344 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 345 boot_params->shared_region_base); 346 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 347 boot_params->shared_region_size); 348 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 349 boot_params->ipc_payload_area_start); 350 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 351 boot_params->ipc_payload_area_size); 352 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 353 boot_params->global_aliased_pio_base); 354 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 355 boot_params->global_aliased_pio_size); 356 357 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 358 boot_params->autoconfig); 359 360 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 361 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 362 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 363 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 364 365 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 366 boot_params->global_memory_allocator_base); 367 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 368 boot_params->global_memory_allocator_size); 369 370 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 371 boot_params->shave_nn_fw_base); 372 373 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 374 boot_params->watchdog_irq_mss); 375 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 376 boot_params->watchdog_irq_nce); 377 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 378 boot_params->host_to_vpu_irq); 379 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 380 boot_params->job_done_irq); 381 382 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 383 boot_params->host_version_id); 384 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 385 boot_params->si_stepping); 386 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 387 boot_params->device_id); 388 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 389 boot_params->feature_exclusion); 390 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 391 boot_params->sku); 392 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 393 boot_params->min_freq_pll_ratio); 394 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 395 boot_params->pn_freq_pll_ratio); 396 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 397 boot_params->max_freq_pll_ratio); 398 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 399 boot_params->default_trace_level); 400 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 401 boot_params->tracing_buff_message_format_mask); 402 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 403 boot_params->trace_destination_mask); 404 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 405 boot_params->trace_hw_component_mask); 406 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 407 boot_params->boot_type); 408 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 409 boot_params->punit_telemetry_sram_base); 410 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 411 boot_params->punit_telemetry_sram_size); 412 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 413 boot_params->vpu_telemetry_enable); 414 } 415 416 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 417 { 418 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 419 420 /* In case of warm boot we only have to reset the entrypoint addr */ 421 if (!ivpu_fw_is_cold_boot(vdev)) { 422 boot_params->save_restore_ret_address = 0; 423 vdev->pm->is_warmboot = true; 424 return; 425 } 426 427 vdev->pm->is_warmboot = false; 428 429 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 430 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 431 boot_params->frequency = ivpu_hw_reg_pll_freq_get(vdev); 432 433 /* 434 * Uncached region of VPU address space, covers IPC buffers, job queues 435 * and log buffers, programmable to L2$ Uncached by VPU MTRR 436 */ 437 boot_params->shared_region_base = vdev->hw->ranges.global_low.start; 438 boot_params->shared_region_size = vdev->hw->ranges.global_low.end - 439 vdev->hw->ranges.global_low.start; 440 441 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 442 boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2; 443 444 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2; 445 boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2; 446 447 boot_params->global_aliased_pio_base = 448 vdev->hw->ranges.global_aliased_pio.start; 449 boot_params->global_aliased_pio_size = 450 ivpu_hw_range_size(&vdev->hw->ranges.global_aliased_pio); 451 452 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 453 boot_params->autoconfig = 1; 454 455 /* Enable L2 cache for first 2GB of high memory */ 456 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 457 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 458 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.global_high.start); 459 460 if (vdev->fw->mem_shave_nn) 461 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 462 463 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 464 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 465 boot_params->si_stepping = ivpu_revision(vdev); 466 boot_params->device_id = ivpu_device_id(vdev); 467 boot_params->feature_exclusion = vdev->hw->tile_fuse; 468 boot_params->sku = vdev->hw->sku; 469 470 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 471 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 472 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 473 474 boot_params->default_trace_level = vdev->fw->trace_level; 475 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 476 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 477 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 478 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 479 boot_params->crit_tracing_buff_size = vdev->fw->mem_log_crit->base.size; 480 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 481 boot_params->verbose_tracing_buff_size = vdev->fw->mem_log_verb->base.size; 482 483 boot_params->punit_telemetry_sram_base = ivpu_hw_reg_telemetry_offset_get(vdev); 484 boot_params->punit_telemetry_sram_size = ivpu_hw_reg_telemetry_size_get(vdev); 485 boot_params->vpu_telemetry_enable = ivpu_hw_reg_telemetry_enable_get(vdev); 486 487 wmb(); /* Flush WC buffers after writing bootparams */ 488 489 ivpu_fw_boot_params_print(vdev, boot_params); 490 } 491