1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 21 #define DRIVER_NAME "intel_vpu" 22 #define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)" 23 #define DRIVER_DATE "20230117" 24 25 #define PCI_DEVICE_ID_MTL 0x7d1d 26 #define PCI_DEVICE_ID_ARL 0xad1d 27 #define PCI_DEVICE_ID_LNL 0x643e 28 29 #define IVPU_HW_37XX 37 30 #define IVPU_HW_40XX 40 31 32 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 33 /* SSID 1 is used by the VPU to represent invalid context */ 34 #define IVPU_USER_CONTEXT_MIN_SSID 2 35 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 36 37 #define IVPU_NUM_ENGINES 2 38 39 #define IVPU_PLATFORM_SILICON 0 40 #define IVPU_PLATFORM_SIMICS 2 41 #define IVPU_PLATFORM_FPGA 3 42 #define IVPU_PLATFORM_INVALID 8 43 44 #define IVPU_DBG_REG BIT(0) 45 #define IVPU_DBG_IRQ BIT(1) 46 #define IVPU_DBG_MMU BIT(2) 47 #define IVPU_DBG_FILE BIT(3) 48 #define IVPU_DBG_MISC BIT(4) 49 #define IVPU_DBG_FW_BOOT BIT(5) 50 #define IVPU_DBG_PM BIT(6) 51 #define IVPU_DBG_IPC BIT(7) 52 #define IVPU_DBG_BO BIT(8) 53 #define IVPU_DBG_JOB BIT(9) 54 #define IVPU_DBG_JSM BIT(10) 55 #define IVPU_DBG_KREF BIT(11) 56 #define IVPU_DBG_RPM BIT(12) 57 58 #define ivpu_err(vdev, fmt, ...) \ 59 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 60 61 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 62 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 63 64 #define ivpu_warn(vdev, fmt, ...) \ 65 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 66 67 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 68 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 69 70 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 71 72 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 73 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 74 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 75 } while (0) 76 77 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 78 79 struct ivpu_wa_table { 80 bool punit_disabled; 81 bool clear_runtime_mem; 82 bool d3hot_after_power_off; 83 bool interrupt_clear_with_0; 84 bool disable_clock_relinquish; 85 }; 86 87 struct ivpu_hw_info; 88 struct ivpu_mmu_info; 89 struct ivpu_fw_info; 90 struct ivpu_ipc_info; 91 struct ivpu_pm_info; 92 93 struct ivpu_device { 94 struct drm_device drm; 95 void __iomem *regb; 96 void __iomem *regv; 97 u32 platform; 98 u32 irq; 99 100 struct ivpu_wa_table wa; 101 struct ivpu_hw_info *hw; 102 struct ivpu_mmu_info *mmu; 103 struct ivpu_fw_info *fw; 104 struct ivpu_ipc_info *ipc; 105 struct ivpu_pm_info *pm; 106 107 struct ivpu_mmu_context gctx; 108 struct xarray context_xa; 109 struct xa_limit context_xa_limit; 110 111 struct xarray submitted_jobs_xa; 112 struct task_struct *job_done_thread; 113 114 atomic64_t unique_id_counter; 115 116 struct { 117 int boot; 118 int jsm; 119 int tdr; 120 int reschedule_suspend; 121 } timeout; 122 }; 123 124 /* 125 * file_priv has its own refcount (ref) that allows user space to close the fd 126 * without blocking even if VPU is still processing some jobs. 127 */ 128 struct ivpu_file_priv { 129 struct kref ref; 130 struct ivpu_device *vdev; 131 struct mutex lock; /* Protects cmdq */ 132 struct ivpu_cmdq *cmdq[IVPU_NUM_ENGINES]; 133 struct ivpu_mmu_context ctx; 134 u32 priority; 135 bool has_mmu_faults; 136 }; 137 138 extern int ivpu_dbg_mask; 139 extern u8 ivpu_pll_min_ratio; 140 extern u8 ivpu_pll_max_ratio; 141 extern bool ivpu_disable_mmu_cont_pages; 142 143 #define IVPU_TEST_MODE_DISABLED 0 144 #define IVPU_TEST_MODE_FW_TEST 1 145 #define IVPU_TEST_MODE_NULL_HW 2 146 extern int ivpu_test_mode; 147 148 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 149 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id); 150 void ivpu_file_priv_put(struct ivpu_file_priv **link); 151 152 int ivpu_boot(struct ivpu_device *vdev); 153 int ivpu_shutdown(struct ivpu_device *vdev); 154 155 static inline u8 ivpu_revision(struct ivpu_device *vdev) 156 { 157 return to_pci_dev(vdev->drm.dev)->revision; 158 } 159 160 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 161 { 162 return to_pci_dev(vdev->drm.dev)->device; 163 } 164 165 static inline int ivpu_hw_gen(struct ivpu_device *vdev) 166 { 167 switch (ivpu_device_id(vdev)) { 168 case PCI_DEVICE_ID_MTL: 169 case PCI_DEVICE_ID_ARL: 170 return IVPU_HW_37XX; 171 case PCI_DEVICE_ID_LNL: 172 return IVPU_HW_40XX; 173 default: 174 ivpu_err(vdev, "Unknown VPU device\n"); 175 return 0; 176 } 177 } 178 179 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 180 { 181 return container_of(dev, struct ivpu_device, drm); 182 } 183 184 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 185 { 186 struct xa_limit ctx_limit = vdev->context_xa_limit; 187 188 return (ctx_limit.max - ctx_limit.min + 1); 189 } 190 191 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 192 { 193 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 194 return vdev->platform; 195 } 196 197 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 198 { 199 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 200 } 201 202 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 203 { 204 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 205 } 206 207 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 208 { 209 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; 210 } 211 212 #endif /* __IVPU_DRV_H__ */ 213