1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 10 #include <drm/drm_accel.h> 11 #include <drm/drm_file.h> 12 #include <drm/drm_gem.h> 13 #include <drm/drm_ioctl.h> 14 #include <drm/drm_prime.h> 15 16 #include "vpu_boot_api.h" 17 #include "ivpu_drv.h" 18 #include "ivpu_fw.h" 19 #include "ivpu_gem.h" 20 #include "ivpu_hw.h" 21 #include "ivpu_ipc.h" 22 #include "ivpu_job.h" 23 #include "ivpu_jsm_msg.h" 24 #include "ivpu_mmu.h" 25 #include "ivpu_mmu_context.h" 26 #include "ivpu_pm.h" 27 28 #ifndef DRIVER_VERSION_STR 29 #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \ 30 __stringify(DRM_IVPU_DRIVER_MINOR) "." 31 #endif 32 33 static const struct drm_driver driver; 34 35 static struct lock_class_key submitted_jobs_xa_lock_class_key; 36 37 int ivpu_dbg_mask; 38 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644); 39 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros."); 40 41 int ivpu_test_mode; 42 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644); 43 MODULE_PARM_DESC(test_mode, "Test mode: 0 - normal operation, 1 - fw unit test, 2 - null hw"); 44 45 u8 ivpu_pll_min_ratio; 46 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644); 47 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency"); 48 49 u8 ivpu_pll_max_ratio = U8_MAX; 50 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644); 51 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set VPU frequency"); 52 53 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv) 54 { 55 struct ivpu_device *vdev = file_priv->vdev; 56 57 kref_get(&file_priv->ref); 58 59 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n", 60 file_priv->ctx.id, kref_read(&file_priv->ref)); 61 62 return file_priv; 63 } 64 65 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id) 66 { 67 struct ivpu_file_priv *file_priv; 68 69 xa_lock_irq(&vdev->context_xa); 70 file_priv = xa_load(&vdev->context_xa, id); 71 /* file_priv may still be in context_xa during file_priv_release() */ 72 if (file_priv && !kref_get_unless_zero(&file_priv->ref)) 73 file_priv = NULL; 74 xa_unlock_irq(&vdev->context_xa); 75 76 if (file_priv) 77 ivpu_dbg(vdev, KREF, "file_priv get by id: ctx %u refcount %u\n", 78 file_priv->ctx.id, kref_read(&file_priv->ref)); 79 80 return file_priv; 81 } 82 83 static void file_priv_release(struct kref *ref) 84 { 85 struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref); 86 struct ivpu_device *vdev = file_priv->vdev; 87 88 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u\n", file_priv->ctx.id); 89 90 ivpu_cmdq_release_all(file_priv); 91 ivpu_bo_remove_all_bos_from_context(&file_priv->ctx); 92 ivpu_jsm_context_release(vdev, file_priv->ctx.id); 93 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); 94 drm_WARN_ON(&vdev->drm, xa_erase_irq(&vdev->context_xa, file_priv->ctx.id) != file_priv); 95 mutex_destroy(&file_priv->lock); 96 kfree(file_priv); 97 } 98 99 void ivpu_file_priv_put(struct ivpu_file_priv **link) 100 { 101 struct ivpu_file_priv *file_priv = *link; 102 struct ivpu_device *vdev = file_priv->vdev; 103 104 drm_WARN_ON(&vdev->drm, !file_priv); 105 106 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n", 107 file_priv->ctx.id, kref_read(&file_priv->ref)); 108 109 *link = NULL; 110 kref_put(&file_priv->ref, file_priv_release); 111 } 112 113 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 114 { 115 struct ivpu_file_priv *file_priv = file->driver_priv; 116 struct ivpu_device *vdev = file_priv->vdev; 117 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev); 118 struct drm_ivpu_param *args = data; 119 int ret = 0; 120 int idx; 121 122 if (!drm_dev_enter(dev, &idx)) 123 return -ENODEV; 124 125 switch (args->param) { 126 case DRM_IVPU_PARAM_DEVICE_ID: 127 args->value = pdev->device; 128 break; 129 case DRM_IVPU_PARAM_DEVICE_REVISION: 130 args->value = pdev->revision; 131 break; 132 case DRM_IVPU_PARAM_PLATFORM_TYPE: 133 args->value = vdev->platform; 134 break; 135 case DRM_IVPU_PARAM_CORE_CLOCK_RATE: 136 args->value = ivpu_hw_reg_pll_freq_get(vdev); 137 break; 138 case DRM_IVPU_PARAM_NUM_CONTEXTS: 139 args->value = ivpu_get_context_count(vdev); 140 break; 141 case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS: 142 args->value = vdev->hw->ranges.user_low.start; 143 break; 144 case DRM_IVPU_PARAM_CONTEXT_PRIORITY: 145 args->value = file_priv->priority; 146 break; 147 case DRM_IVPU_PARAM_CONTEXT_ID: 148 args->value = file_priv->ctx.id; 149 break; 150 case DRM_IVPU_PARAM_FW_API_VERSION: 151 if (args->index < VPU_FW_API_VER_NUM) { 152 struct vpu_firmware_header *fw_hdr; 153 154 fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data; 155 args->value = fw_hdr->api_version[args->index]; 156 } else { 157 ret = -EINVAL; 158 } 159 break; 160 case DRM_IVPU_PARAM_ENGINE_HEARTBEAT: 161 ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value); 162 break; 163 case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID: 164 args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter); 165 break; 166 case DRM_IVPU_PARAM_TILE_CONFIG: 167 args->value = vdev->hw->tile_fuse; 168 break; 169 case DRM_IVPU_PARAM_SKU: 170 args->value = vdev->hw->sku; 171 break; 172 default: 173 ret = -EINVAL; 174 break; 175 } 176 177 drm_dev_exit(idx); 178 return ret; 179 } 180 181 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 182 { 183 struct ivpu_file_priv *file_priv = file->driver_priv; 184 struct drm_ivpu_param *args = data; 185 int ret = 0; 186 187 switch (args->param) { 188 case DRM_IVPU_PARAM_CONTEXT_PRIORITY: 189 if (args->value <= DRM_IVPU_CONTEXT_PRIORITY_REALTIME) 190 file_priv->priority = args->value; 191 else 192 ret = -EINVAL; 193 break; 194 default: 195 ret = -EINVAL; 196 } 197 198 return ret; 199 } 200 201 static int ivpu_open(struct drm_device *dev, struct drm_file *file) 202 { 203 struct ivpu_device *vdev = to_ivpu_device(dev); 204 struct ivpu_file_priv *file_priv; 205 u32 ctx_id; 206 void *old; 207 int ret; 208 209 ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, NULL, vdev->context_xa_limit, GFP_KERNEL); 210 if (ret) { 211 ivpu_err(vdev, "Failed to allocate context id: %d\n", ret); 212 return ret; 213 } 214 215 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); 216 if (!file_priv) { 217 ret = -ENOMEM; 218 goto err_xa_erase; 219 } 220 221 file_priv->vdev = vdev; 222 file_priv->priority = DRM_IVPU_CONTEXT_PRIORITY_NORMAL; 223 kref_init(&file_priv->ref); 224 mutex_init(&file_priv->lock); 225 226 ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id); 227 if (ret) 228 goto err_mutex_destroy; 229 230 old = xa_store_irq(&vdev->context_xa, ctx_id, file_priv, GFP_KERNEL); 231 if (xa_is_err(old)) { 232 ret = xa_err(old); 233 ivpu_err(vdev, "Failed to store context %u: %d\n", ctx_id, ret); 234 goto err_ctx_fini; 235 } 236 237 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", 238 ctx_id, current->comm, task_pid_nr(current)); 239 240 file->driver_priv = file_priv; 241 return 0; 242 243 err_ctx_fini: 244 ivpu_mmu_user_context_fini(vdev, &file_priv->ctx); 245 err_mutex_destroy: 246 mutex_destroy(&file_priv->lock); 247 kfree(file_priv); 248 err_xa_erase: 249 xa_erase_irq(&vdev->context_xa, ctx_id); 250 return ret; 251 } 252 253 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file) 254 { 255 struct ivpu_file_priv *file_priv = file->driver_priv; 256 struct ivpu_device *vdev = to_ivpu_device(dev); 257 258 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", 259 file_priv->ctx.id, current->comm, task_pid_nr(current)); 260 261 ivpu_file_priv_put(&file_priv); 262 } 263 264 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = { 265 DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0), 266 DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0), 267 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0), 268 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0), 269 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0), 270 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0), 271 }; 272 273 static int ivpu_wait_for_ready(struct ivpu_device *vdev) 274 { 275 struct ivpu_ipc_consumer cons; 276 struct ivpu_ipc_hdr ipc_hdr; 277 unsigned long timeout; 278 int ret; 279 280 if (ivpu_test_mode == IVPU_TEST_MODE_FW_TEST) 281 return 0; 282 283 ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG); 284 285 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot); 286 while (1) { 287 ret = ivpu_ipc_irq_handler(vdev); 288 if (ret) 289 break; 290 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0); 291 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout)) 292 break; 293 294 cond_resched(); 295 } 296 297 ivpu_ipc_consumer_del(vdev, &cons); 298 299 if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) { 300 ivpu_err(vdev, "Invalid VPU ready message: 0x%x\n", 301 ipc_hdr.data_addr); 302 return -EIO; 303 } 304 305 if (!ret) 306 ivpu_info(vdev, "VPU ready message received successfully\n"); 307 else 308 ivpu_hw_diagnose_failure(vdev); 309 310 return ret; 311 } 312 313 /** 314 * ivpu_boot() - Start VPU firmware 315 * @vdev: VPU device 316 * 317 * This function is paired with ivpu_shutdown() but it doesn't power up the 318 * VPU because power up has to be called very early in ivpu_probe(). 319 */ 320 int ivpu_boot(struct ivpu_device *vdev) 321 { 322 int ret; 323 324 /* Update boot params located at first 4KB of FW memory */ 325 ivpu_fw_boot_params_setup(vdev, vdev->fw->mem->kvaddr); 326 327 ret = ivpu_hw_boot_fw(vdev); 328 if (ret) { 329 ivpu_err(vdev, "Failed to start the firmware: %d\n", ret); 330 return ret; 331 } 332 333 ret = ivpu_wait_for_ready(vdev); 334 if (ret) { 335 ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret); 336 return ret; 337 } 338 339 ivpu_hw_irq_clear(vdev); 340 enable_irq(vdev->irq); 341 ivpu_hw_irq_enable(vdev); 342 ivpu_ipc_enable(vdev); 343 return 0; 344 } 345 346 int ivpu_shutdown(struct ivpu_device *vdev) 347 { 348 int ret; 349 350 ivpu_hw_irq_disable(vdev); 351 disable_irq(vdev->irq); 352 ivpu_ipc_disable(vdev); 353 ivpu_mmu_disable(vdev); 354 355 ret = ivpu_hw_power_down(vdev); 356 if (ret) 357 ivpu_warn(vdev, "Failed to power down HW: %d\n", ret); 358 359 return ret; 360 } 361 362 static const struct file_operations ivpu_fops = { 363 .owner = THIS_MODULE, 364 DRM_ACCEL_FOPS, 365 }; 366 367 static const struct drm_driver driver = { 368 .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL, 369 370 .open = ivpu_open, 371 .postclose = ivpu_postclose, 372 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 373 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 374 .gem_prime_import = ivpu_gem_prime_import, 375 .gem_prime_mmap = drm_gem_prime_mmap, 376 377 .ioctls = ivpu_drm_ioctls, 378 .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls), 379 .fops = &ivpu_fops, 380 381 .name = DRIVER_NAME, 382 .desc = DRIVER_DESC, 383 .date = DRIVER_DATE, 384 .major = DRM_IVPU_DRIVER_MAJOR, 385 .minor = DRM_IVPU_DRIVER_MINOR, 386 }; 387 388 static int ivpu_irq_init(struct ivpu_device *vdev) 389 { 390 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev); 391 int ret; 392 393 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX); 394 if (ret < 0) { 395 ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret); 396 return ret; 397 } 398 399 vdev->irq = pci_irq_vector(pdev, 0); 400 401 ret = devm_request_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler, 402 IRQF_NO_AUTOEN, DRIVER_NAME, vdev); 403 if (ret) 404 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret); 405 406 return ret; 407 } 408 409 static int ivpu_pci_init(struct ivpu_device *vdev) 410 { 411 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev); 412 struct resource *bar0 = &pdev->resource[0]; 413 struct resource *bar4 = &pdev->resource[4]; 414 int ret; 415 416 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); 417 vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0); 418 if (IS_ERR(vdev->regv)) { 419 ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv); 420 return PTR_ERR(vdev->regv); 421 } 422 423 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); 424 vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4); 425 if (IS_ERR(vdev->regb)) { 426 ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb); 427 return PTR_ERR(vdev->regb); 428 } 429 430 ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(38)); 431 if (ret) { 432 ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret); 433 return ret; 434 } 435 dma_set_max_seg_size(vdev->drm.dev, UINT_MAX); 436 437 /* Clear any pending errors */ 438 pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f); 439 440 /* VPU MTL does not require PCI spec 10m D3hot delay */ 441 if (ivpu_is_mtl(vdev)) 442 pdev->d3hot_delay = 0; 443 444 ret = pcim_enable_device(pdev); 445 if (ret) { 446 ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret); 447 return ret; 448 } 449 450 pci_set_master(pdev); 451 452 return 0; 453 } 454 455 static int ivpu_dev_init(struct ivpu_device *vdev) 456 { 457 int ret; 458 459 vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL); 460 if (!vdev->hw) 461 return -ENOMEM; 462 463 vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL); 464 if (!vdev->mmu) 465 return -ENOMEM; 466 467 vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL); 468 if (!vdev->fw) 469 return -ENOMEM; 470 471 vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL); 472 if (!vdev->ipc) 473 return -ENOMEM; 474 475 vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL); 476 if (!vdev->pm) 477 return -ENOMEM; 478 479 vdev->hw->ops = &ivpu_hw_mtl_ops; 480 vdev->platform = IVPU_PLATFORM_INVALID; 481 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID; 482 vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID; 483 atomic64_set(&vdev->unique_id_counter, 0); 484 xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC); 485 xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1); 486 lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key); 487 488 ret = ivpu_pci_init(vdev); 489 if (ret) { 490 ivpu_err(vdev, "Failed to initialize PCI device: %d\n", ret); 491 goto err_xa_destroy; 492 } 493 494 ret = ivpu_irq_init(vdev); 495 if (ret) { 496 ivpu_err(vdev, "Failed to initialize IRQs: %d\n", ret); 497 goto err_xa_destroy; 498 } 499 500 /* Init basic HW info based on buttress registers which are accessible before power up */ 501 ret = ivpu_hw_info_init(vdev); 502 if (ret) { 503 ivpu_err(vdev, "Failed to initialize HW info: %d\n", ret); 504 goto err_xa_destroy; 505 } 506 507 /* Power up early so the rest of init code can access VPU registers */ 508 ret = ivpu_hw_power_up(vdev); 509 if (ret) { 510 ivpu_err(vdev, "Failed to power up HW: %d\n", ret); 511 goto err_xa_destroy; 512 } 513 514 ret = ivpu_mmu_global_context_init(vdev); 515 if (ret) { 516 ivpu_err(vdev, "Failed to initialize global MMU context: %d\n", ret); 517 goto err_power_down; 518 } 519 520 ret = ivpu_mmu_init(vdev); 521 if (ret) { 522 ivpu_err(vdev, "Failed to initialize MMU device: %d\n", ret); 523 goto err_mmu_gctx_fini; 524 } 525 526 ret = ivpu_fw_init(vdev); 527 if (ret) { 528 ivpu_err(vdev, "Failed to initialize firmware: %d\n", ret); 529 goto err_mmu_gctx_fini; 530 } 531 532 ret = ivpu_ipc_init(vdev); 533 if (ret) { 534 ivpu_err(vdev, "Failed to initialize IPC: %d\n", ret); 535 goto err_fw_fini; 536 } 537 538 ret = ivpu_pm_init(vdev); 539 if (ret) { 540 ivpu_err(vdev, "Failed to initialize PM: %d\n", ret); 541 goto err_ipc_fini; 542 } 543 544 ret = ivpu_job_done_thread_init(vdev); 545 if (ret) { 546 ivpu_err(vdev, "Failed to initialize job done thread: %d\n", ret); 547 goto err_ipc_fini; 548 } 549 550 ret = ivpu_fw_load(vdev); 551 if (ret) { 552 ivpu_err(vdev, "Failed to load firmware: %d\n", ret); 553 goto err_job_done_thread_fini; 554 } 555 556 ret = ivpu_boot(vdev); 557 if (ret) { 558 ivpu_err(vdev, "Failed to boot: %d\n", ret); 559 goto err_job_done_thread_fini; 560 } 561 562 ivpu_pm_enable(vdev); 563 564 return 0; 565 566 err_job_done_thread_fini: 567 ivpu_job_done_thread_fini(vdev); 568 err_ipc_fini: 569 ivpu_ipc_fini(vdev); 570 err_fw_fini: 571 ivpu_fw_fini(vdev); 572 err_mmu_gctx_fini: 573 ivpu_mmu_global_context_fini(vdev); 574 err_power_down: 575 ivpu_hw_power_down(vdev); 576 if (IVPU_WA(d3hot_after_power_off)) 577 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot); 578 err_xa_destroy: 579 xa_destroy(&vdev->submitted_jobs_xa); 580 xa_destroy(&vdev->context_xa); 581 return ret; 582 } 583 584 static void ivpu_dev_fini(struct ivpu_device *vdev) 585 { 586 ivpu_pm_disable(vdev); 587 ivpu_shutdown(vdev); 588 if (IVPU_WA(d3hot_after_power_off)) 589 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot); 590 ivpu_job_done_thread_fini(vdev); 591 ivpu_pm_cancel_recovery(vdev); 592 593 ivpu_ipc_fini(vdev); 594 ivpu_fw_fini(vdev); 595 ivpu_mmu_global_context_fini(vdev); 596 597 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa)); 598 xa_destroy(&vdev->submitted_jobs_xa); 599 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa)); 600 xa_destroy(&vdev->context_xa); 601 } 602 603 static struct pci_device_id ivpu_pci_ids[] = { 604 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) }, 605 { } 606 }; 607 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids); 608 609 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 610 { 611 struct ivpu_device *vdev; 612 int ret; 613 614 vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm); 615 if (IS_ERR(vdev)) 616 return PTR_ERR(vdev); 617 618 pci_set_drvdata(pdev, vdev); 619 620 ret = ivpu_dev_init(vdev); 621 if (ret) { 622 dev_err(&pdev->dev, "Failed to initialize VPU device: %d\n", ret); 623 return ret; 624 } 625 626 ret = drm_dev_register(&vdev->drm, 0); 627 if (ret) { 628 dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret); 629 ivpu_dev_fini(vdev); 630 } 631 632 return ret; 633 } 634 635 static void ivpu_remove(struct pci_dev *pdev) 636 { 637 struct ivpu_device *vdev = pci_get_drvdata(pdev); 638 639 drm_dev_unplug(&vdev->drm); 640 ivpu_dev_fini(vdev); 641 } 642 643 static const struct dev_pm_ops ivpu_drv_pci_pm = { 644 SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb) 645 SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL) 646 }; 647 648 static const struct pci_error_handlers ivpu_drv_pci_err = { 649 .reset_prepare = ivpu_pm_reset_prepare_cb, 650 .reset_done = ivpu_pm_reset_done_cb, 651 }; 652 653 static struct pci_driver ivpu_pci_driver = { 654 .name = KBUILD_MODNAME, 655 .id_table = ivpu_pci_ids, 656 .probe = ivpu_probe, 657 .remove = ivpu_remove, 658 .driver = { 659 .pm = &ivpu_drv_pci_pm, 660 }, 661 .err_handler = &ivpu_drv_pci_err, 662 }; 663 664 module_pci_driver(ivpu_pci_driver); 665 666 MODULE_AUTHOR("Intel Corporation"); 667 MODULE_DESCRIPTION(DRIVER_DESC); 668 MODULE_LICENSE("GPL and additional rights"); 669 MODULE_VERSION(DRIVER_VERSION_STR); 670