xref: /openbmc/linux/drivers/accel/ivpu/ivpu_drv.c (revision edde4cae)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2020-2023 Intel Corporation
4  */
5 
6 #include <linux/firmware.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 
10 #include <drm/drm_accel.h>
11 #include <drm/drm_file.h>
12 #include <drm/drm_gem.h>
13 #include <drm/drm_ioctl.h>
14 #include <drm/drm_prime.h>
15 
16 #include "vpu_boot_api.h"
17 #include "ivpu_debugfs.h"
18 #include "ivpu_drv.h"
19 #include "ivpu_fw.h"
20 #include "ivpu_gem.h"
21 #include "ivpu_hw.h"
22 #include "ivpu_ipc.h"
23 #include "ivpu_job.h"
24 #include "ivpu_jsm_msg.h"
25 #include "ivpu_mmu.h"
26 #include "ivpu_mmu_context.h"
27 #include "ivpu_pm.h"
28 
29 #ifndef DRIVER_VERSION_STR
30 #define DRIVER_VERSION_STR __stringify(DRM_IVPU_DRIVER_MAJOR) "." \
31 			   __stringify(DRM_IVPU_DRIVER_MINOR) "."
32 #endif
33 
34 static const struct drm_driver driver;
35 
36 static struct lock_class_key submitted_jobs_xa_lock_class_key;
37 
38 int ivpu_dbg_mask;
39 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
40 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
41 
42 int ivpu_test_mode;
43 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
44 MODULE_PARM_DESC(test_mode, "Test mode: 0 - normal operation, 1 - fw unit test, 2 - null hw");
45 
46 u8 ivpu_pll_min_ratio;
47 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
48 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set VPU frequency");
49 
50 u8 ivpu_pll_max_ratio = U8_MAX;
51 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
52 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set VPU frequency");
53 
54 bool ivpu_disable_mmu_cont_pages;
55 module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0644);
56 MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
57 
58 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
59 {
60 	struct ivpu_device *vdev = file_priv->vdev;
61 
62 	kref_get(&file_priv->ref);
63 
64 	ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
65 		 file_priv->ctx.id, kref_read(&file_priv->ref));
66 
67 	return file_priv;
68 }
69 
70 struct ivpu_file_priv *ivpu_file_priv_get_by_ctx_id(struct ivpu_device *vdev, unsigned long id)
71 {
72 	struct ivpu_file_priv *file_priv;
73 
74 	xa_lock_irq(&vdev->context_xa);
75 	file_priv = xa_load(&vdev->context_xa, id);
76 	/* file_priv may still be in context_xa during file_priv_release() */
77 	if (file_priv && !kref_get_unless_zero(&file_priv->ref))
78 		file_priv = NULL;
79 	xa_unlock_irq(&vdev->context_xa);
80 
81 	if (file_priv)
82 		ivpu_dbg(vdev, KREF, "file_priv get by id: ctx %u refcount %u\n",
83 			 file_priv->ctx.id, kref_read(&file_priv->ref));
84 
85 	return file_priv;
86 }
87 
88 static void file_priv_release(struct kref *ref)
89 {
90 	struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
91 	struct ivpu_device *vdev = file_priv->vdev;
92 
93 	ivpu_dbg(vdev, FILE, "file_priv release: ctx %u\n", file_priv->ctx.id);
94 
95 	ivpu_cmdq_release_all(file_priv);
96 	ivpu_bo_remove_all_bos_from_context(&file_priv->ctx);
97 	ivpu_jsm_context_release(vdev, file_priv->ctx.id);
98 	ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
99 	drm_WARN_ON(&vdev->drm, xa_erase_irq(&vdev->context_xa, file_priv->ctx.id) != file_priv);
100 	mutex_destroy(&file_priv->lock);
101 	kfree(file_priv);
102 }
103 
104 void ivpu_file_priv_put(struct ivpu_file_priv **link)
105 {
106 	struct ivpu_file_priv *file_priv = *link;
107 	struct ivpu_device *vdev = file_priv->vdev;
108 
109 	drm_WARN_ON(&vdev->drm, !file_priv);
110 
111 	ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
112 		 file_priv->ctx.id, kref_read(&file_priv->ref));
113 
114 	*link = NULL;
115 	kref_put(&file_priv->ref, file_priv_release);
116 }
117 
118 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
119 {
120 	struct ivpu_file_priv *file_priv = file->driver_priv;
121 	struct ivpu_device *vdev = file_priv->vdev;
122 	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
123 	struct drm_ivpu_param *args = data;
124 	int ret = 0;
125 	int idx;
126 
127 	if (!drm_dev_enter(dev, &idx))
128 		return -ENODEV;
129 
130 	switch (args->param) {
131 	case DRM_IVPU_PARAM_DEVICE_ID:
132 		args->value = pdev->device;
133 		break;
134 	case DRM_IVPU_PARAM_DEVICE_REVISION:
135 		args->value = pdev->revision;
136 		break;
137 	case DRM_IVPU_PARAM_PLATFORM_TYPE:
138 		args->value = vdev->platform;
139 		break;
140 	case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
141 		args->value = ivpu_hw_reg_pll_freq_get(vdev);
142 		break;
143 	case DRM_IVPU_PARAM_NUM_CONTEXTS:
144 		args->value = ivpu_get_context_count(vdev);
145 		break;
146 	case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
147 		args->value = vdev->hw->ranges.user_low.start;
148 		break;
149 	case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
150 		args->value = file_priv->priority;
151 		break;
152 	case DRM_IVPU_PARAM_CONTEXT_ID:
153 		args->value = file_priv->ctx.id;
154 		break;
155 	case DRM_IVPU_PARAM_FW_API_VERSION:
156 		if (args->index < VPU_FW_API_VER_NUM) {
157 			struct vpu_firmware_header *fw_hdr;
158 
159 			fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
160 			args->value = fw_hdr->api_version[args->index];
161 		} else {
162 			ret = -EINVAL;
163 		}
164 		break;
165 	case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
166 		ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
167 		break;
168 	case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
169 		args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
170 		break;
171 	case DRM_IVPU_PARAM_TILE_CONFIG:
172 		args->value = vdev->hw->tile_fuse;
173 		break;
174 	case DRM_IVPU_PARAM_SKU:
175 		args->value = vdev->hw->sku;
176 		break;
177 	default:
178 		ret = -EINVAL;
179 		break;
180 	}
181 
182 	drm_dev_exit(idx);
183 	return ret;
184 }
185 
186 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
187 {
188 	struct ivpu_file_priv *file_priv = file->driver_priv;
189 	struct drm_ivpu_param *args = data;
190 	int ret = 0;
191 
192 	switch (args->param) {
193 	case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
194 		if (args->value <= DRM_IVPU_CONTEXT_PRIORITY_REALTIME)
195 			file_priv->priority = args->value;
196 		else
197 			ret = -EINVAL;
198 		break;
199 	default:
200 		ret = -EINVAL;
201 	}
202 
203 	return ret;
204 }
205 
206 static int ivpu_open(struct drm_device *dev, struct drm_file *file)
207 {
208 	struct ivpu_device *vdev = to_ivpu_device(dev);
209 	struct ivpu_file_priv *file_priv;
210 	u32 ctx_id;
211 	void *old;
212 	int ret;
213 
214 	ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, NULL, vdev->context_xa_limit, GFP_KERNEL);
215 	if (ret) {
216 		ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
217 		return ret;
218 	}
219 
220 	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
221 	if (!file_priv) {
222 		ret = -ENOMEM;
223 		goto err_xa_erase;
224 	}
225 
226 	file_priv->vdev = vdev;
227 	file_priv->priority = DRM_IVPU_CONTEXT_PRIORITY_NORMAL;
228 	kref_init(&file_priv->ref);
229 	mutex_init(&file_priv->lock);
230 
231 	ret = ivpu_mmu_user_context_init(vdev, &file_priv->ctx, ctx_id);
232 	if (ret)
233 		goto err_mutex_destroy;
234 
235 	old = xa_store_irq(&vdev->context_xa, ctx_id, file_priv, GFP_KERNEL);
236 	if (xa_is_err(old)) {
237 		ret = xa_err(old);
238 		ivpu_err(vdev, "Failed to store context %u: %d\n", ctx_id, ret);
239 		goto err_ctx_fini;
240 	}
241 
242 	ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
243 		 ctx_id, current->comm, task_pid_nr(current));
244 
245 	file->driver_priv = file_priv;
246 	return 0;
247 
248 err_ctx_fini:
249 	ivpu_mmu_user_context_fini(vdev, &file_priv->ctx);
250 err_mutex_destroy:
251 	mutex_destroy(&file_priv->lock);
252 	kfree(file_priv);
253 err_xa_erase:
254 	xa_erase_irq(&vdev->context_xa, ctx_id);
255 	return ret;
256 }
257 
258 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
259 {
260 	struct ivpu_file_priv *file_priv = file->driver_priv;
261 	struct ivpu_device *vdev = to_ivpu_device(dev);
262 
263 	ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
264 		 file_priv->ctx.id, current->comm, task_pid_nr(current));
265 
266 	ivpu_file_priv_put(&file_priv);
267 }
268 
269 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
270 	DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
271 	DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
272 	DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
273 	DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
274 	DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
275 	DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
276 };
277 
278 static int ivpu_wait_for_ready(struct ivpu_device *vdev)
279 {
280 	struct ivpu_ipc_consumer cons;
281 	struct ivpu_ipc_hdr ipc_hdr;
282 	unsigned long timeout;
283 	int ret;
284 
285 	if (ivpu_test_mode == IVPU_TEST_MODE_FW_TEST)
286 		return 0;
287 
288 	ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG);
289 
290 	timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
291 	while (1) {
292 		ret = ivpu_ipc_irq_handler(vdev);
293 		if (ret)
294 			break;
295 		ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
296 		if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
297 			break;
298 
299 		cond_resched();
300 	}
301 
302 	ivpu_ipc_consumer_del(vdev, &cons);
303 
304 	if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
305 		ivpu_err(vdev, "Invalid VPU ready message: 0x%x\n",
306 			 ipc_hdr.data_addr);
307 		return -EIO;
308 	}
309 
310 	if (!ret)
311 		ivpu_info(vdev, "VPU ready message received successfully\n");
312 	else
313 		ivpu_hw_diagnose_failure(vdev);
314 
315 	return ret;
316 }
317 
318 /**
319  * ivpu_boot() - Start VPU firmware
320  * @vdev: VPU device
321  *
322  * This function is paired with ivpu_shutdown() but it doesn't power up the
323  * VPU because power up has to be called very early in ivpu_probe().
324  */
325 int ivpu_boot(struct ivpu_device *vdev)
326 {
327 	int ret;
328 
329 	/* Update boot params located at first 4KB of FW memory */
330 	ivpu_fw_boot_params_setup(vdev, vdev->fw->mem->kvaddr);
331 
332 	ret = ivpu_hw_boot_fw(vdev);
333 	if (ret) {
334 		ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
335 		return ret;
336 	}
337 
338 	ret = ivpu_wait_for_ready(vdev);
339 	if (ret) {
340 		ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
341 		return ret;
342 	}
343 
344 	ivpu_hw_irq_clear(vdev);
345 	enable_irq(vdev->irq);
346 	ivpu_hw_irq_enable(vdev);
347 	ivpu_ipc_enable(vdev);
348 	return 0;
349 }
350 
351 int ivpu_shutdown(struct ivpu_device *vdev)
352 {
353 	int ret;
354 
355 	ivpu_hw_irq_disable(vdev);
356 	disable_irq(vdev->irq);
357 	ivpu_ipc_disable(vdev);
358 	ivpu_mmu_disable(vdev);
359 
360 	ret = ivpu_hw_power_down(vdev);
361 	if (ret)
362 		ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
363 
364 	return ret;
365 }
366 
367 static const struct file_operations ivpu_fops = {
368 	.owner		= THIS_MODULE,
369 	DRM_ACCEL_FOPS,
370 };
371 
372 static const struct drm_driver driver = {
373 	.driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
374 
375 	.open = ivpu_open,
376 	.postclose = ivpu_postclose,
377 	.gem_prime_import = ivpu_gem_prime_import,
378 
379 #if defined(CONFIG_DEBUG_FS)
380 	.debugfs_init = ivpu_debugfs_init,
381 #endif
382 
383 	.ioctls = ivpu_drm_ioctls,
384 	.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
385 	.fops = &ivpu_fops,
386 
387 	.name = DRIVER_NAME,
388 	.desc = DRIVER_DESC,
389 	.date = DRIVER_DATE,
390 	.major = DRM_IVPU_DRIVER_MAJOR,
391 	.minor = DRM_IVPU_DRIVER_MINOR,
392 };
393 
394 static int ivpu_irq_init(struct ivpu_device *vdev)
395 {
396 	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
397 	int ret;
398 
399 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
400 	if (ret < 0) {
401 		ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
402 		return ret;
403 	}
404 
405 	vdev->irq = pci_irq_vector(pdev, 0);
406 
407 	ret = devm_request_irq(vdev->drm.dev, vdev->irq, vdev->hw->ops->irq_handler,
408 			       IRQF_NO_AUTOEN, DRIVER_NAME, vdev);
409 	if (ret)
410 		ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
411 
412 	return ret;
413 }
414 
415 static int ivpu_pci_init(struct ivpu_device *vdev)
416 {
417 	struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
418 	struct resource *bar0 = &pdev->resource[0];
419 	struct resource *bar4 = &pdev->resource[4];
420 	int ret;
421 
422 	ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
423 	vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
424 	if (IS_ERR(vdev->regv)) {
425 		ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
426 		return PTR_ERR(vdev->regv);
427 	}
428 
429 	ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
430 	vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
431 	if (IS_ERR(vdev->regb)) {
432 		ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
433 		return PTR_ERR(vdev->regb);
434 	}
435 
436 	ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
437 	if (ret) {
438 		ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
439 		return ret;
440 	}
441 	dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
442 
443 	/* Clear any pending errors */
444 	pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
445 
446 	/* VPU MTL does not require PCI spec 10m D3hot delay */
447 	if (ivpu_is_mtl(vdev))
448 		pdev->d3hot_delay = 0;
449 
450 	ret = pcim_enable_device(pdev);
451 	if (ret) {
452 		ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
453 		return ret;
454 	}
455 
456 	pci_set_master(pdev);
457 
458 	return 0;
459 }
460 
461 static int ivpu_dev_init(struct ivpu_device *vdev)
462 {
463 	int ret;
464 
465 	vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
466 	if (!vdev->hw)
467 		return -ENOMEM;
468 
469 	vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
470 	if (!vdev->mmu)
471 		return -ENOMEM;
472 
473 	vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
474 	if (!vdev->fw)
475 		return -ENOMEM;
476 
477 	vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
478 	if (!vdev->ipc)
479 		return -ENOMEM;
480 
481 	vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
482 	if (!vdev->pm)
483 		return -ENOMEM;
484 
485 	vdev->hw->ops = &ivpu_hw_mtl_ops;
486 	vdev->hw->dma_bits = 38;
487 
488 	vdev->platform = IVPU_PLATFORM_INVALID;
489 	vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
490 	vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
491 	atomic64_set(&vdev->unique_id_counter, 0);
492 	xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC);
493 	xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
494 	lockdep_set_class(&vdev->submitted_jobs_xa.xa_lock, &submitted_jobs_xa_lock_class_key);
495 
496 	ret = ivpu_pci_init(vdev);
497 	if (ret) {
498 		ivpu_err(vdev, "Failed to initialize PCI device: %d\n", ret);
499 		goto err_xa_destroy;
500 	}
501 
502 	ret = ivpu_irq_init(vdev);
503 	if (ret) {
504 		ivpu_err(vdev, "Failed to initialize IRQs: %d\n", ret);
505 		goto err_xa_destroy;
506 	}
507 
508 	/* Init basic HW info based on buttress registers which are accessible before power up */
509 	ret = ivpu_hw_info_init(vdev);
510 	if (ret) {
511 		ivpu_err(vdev, "Failed to initialize HW info: %d\n", ret);
512 		goto err_xa_destroy;
513 	}
514 
515 	/* Power up early so the rest of init code can access VPU registers */
516 	ret = ivpu_hw_power_up(vdev);
517 	if (ret) {
518 		ivpu_err(vdev, "Failed to power up HW: %d\n", ret);
519 		goto err_xa_destroy;
520 	}
521 
522 	ret = ivpu_mmu_global_context_init(vdev);
523 	if (ret) {
524 		ivpu_err(vdev, "Failed to initialize global MMU context: %d\n", ret);
525 		goto err_power_down;
526 	}
527 
528 	ret = ivpu_mmu_init(vdev);
529 	if (ret) {
530 		ivpu_err(vdev, "Failed to initialize MMU device: %d\n", ret);
531 		goto err_mmu_gctx_fini;
532 	}
533 
534 	ret = ivpu_fw_init(vdev);
535 	if (ret) {
536 		ivpu_err(vdev, "Failed to initialize firmware: %d\n", ret);
537 		goto err_mmu_gctx_fini;
538 	}
539 
540 	ret = ivpu_ipc_init(vdev);
541 	if (ret) {
542 		ivpu_err(vdev, "Failed to initialize IPC: %d\n", ret);
543 		goto err_fw_fini;
544 	}
545 
546 	ret = ivpu_pm_init(vdev);
547 	if (ret) {
548 		ivpu_err(vdev, "Failed to initialize PM: %d\n", ret);
549 		goto err_ipc_fini;
550 	}
551 
552 	ret = ivpu_job_done_thread_init(vdev);
553 	if (ret) {
554 		ivpu_err(vdev, "Failed to initialize job done thread: %d\n", ret);
555 		goto err_ipc_fini;
556 	}
557 
558 	ret = ivpu_fw_load(vdev);
559 	if (ret) {
560 		ivpu_err(vdev, "Failed to load firmware: %d\n", ret);
561 		goto err_job_done_thread_fini;
562 	}
563 
564 	ret = ivpu_boot(vdev);
565 	if (ret) {
566 		ivpu_err(vdev, "Failed to boot: %d\n", ret);
567 		goto err_job_done_thread_fini;
568 	}
569 
570 	ivpu_pm_enable(vdev);
571 
572 	return 0;
573 
574 err_job_done_thread_fini:
575 	ivpu_job_done_thread_fini(vdev);
576 err_ipc_fini:
577 	ivpu_ipc_fini(vdev);
578 err_fw_fini:
579 	ivpu_fw_fini(vdev);
580 err_mmu_gctx_fini:
581 	ivpu_mmu_global_context_fini(vdev);
582 err_power_down:
583 	ivpu_hw_power_down(vdev);
584 	if (IVPU_WA(d3hot_after_power_off))
585 		pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
586 err_xa_destroy:
587 	xa_destroy(&vdev->submitted_jobs_xa);
588 	xa_destroy(&vdev->context_xa);
589 	return ret;
590 }
591 
592 static void ivpu_dev_fini(struct ivpu_device *vdev)
593 {
594 	ivpu_pm_disable(vdev);
595 	ivpu_shutdown(vdev);
596 	if (IVPU_WA(d3hot_after_power_off))
597 		pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
598 	ivpu_job_done_thread_fini(vdev);
599 	ivpu_pm_cancel_recovery(vdev);
600 
601 	ivpu_ipc_fini(vdev);
602 	ivpu_fw_fini(vdev);
603 	ivpu_mmu_global_context_fini(vdev);
604 
605 	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
606 	xa_destroy(&vdev->submitted_jobs_xa);
607 	drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
608 	xa_destroy(&vdev->context_xa);
609 }
610 
611 static struct pci_device_id ivpu_pci_ids[] = {
612 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
613 	{ }
614 };
615 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
616 
617 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
618 {
619 	struct ivpu_device *vdev;
620 	int ret;
621 
622 	vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
623 	if (IS_ERR(vdev))
624 		return PTR_ERR(vdev);
625 
626 	pci_set_drvdata(pdev, vdev);
627 
628 	ret = ivpu_dev_init(vdev);
629 	if (ret) {
630 		dev_err(&pdev->dev, "Failed to initialize VPU device: %d\n", ret);
631 		return ret;
632 	}
633 
634 	ret = drm_dev_register(&vdev->drm, 0);
635 	if (ret) {
636 		dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
637 		ivpu_dev_fini(vdev);
638 	}
639 
640 	return ret;
641 }
642 
643 static void ivpu_remove(struct pci_dev *pdev)
644 {
645 	struct ivpu_device *vdev = pci_get_drvdata(pdev);
646 
647 	drm_dev_unplug(&vdev->drm);
648 	ivpu_dev_fini(vdev);
649 }
650 
651 static const struct dev_pm_ops ivpu_drv_pci_pm = {
652 	SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
653 	SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
654 };
655 
656 static const struct pci_error_handlers ivpu_drv_pci_err = {
657 	.reset_prepare = ivpu_pm_reset_prepare_cb,
658 	.reset_done = ivpu_pm_reset_done_cb,
659 };
660 
661 static struct pci_driver ivpu_pci_driver = {
662 	.name = KBUILD_MODNAME,
663 	.id_table = ivpu_pci_ids,
664 	.probe = ivpu_probe,
665 	.remove = ivpu_remove,
666 	.driver = {
667 		.pm = &ivpu_drv_pci_pm,
668 	},
669 	.err_handler = &ivpu_drv_pci_err,
670 };
671 
672 module_pci_driver(ivpu_pci_driver);
673 
674 MODULE_AUTHOR("Intel Corporation");
675 MODULE_DESCRIPTION(DRIVER_DESC);
676 MODULE_LICENSE("GPL and additional rights");
677 MODULE_VERSION(DRIVER_VERSION_STR);
678