1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_TPC0_QM_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_TPC0_QM_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * TPC0_QM (Prototype: QMAN) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* TPC0_QM_GLBL_CFG0 */ 23*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 24*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1 25*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1 26*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2 27*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2 28*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4 29*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3 30*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay /* TPC0_QM_GLBL_CFG1 */ 33*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 34*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 35*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 36*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 37*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2 38*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4 39*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 40*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 41*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 42*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 43*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 44*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 45*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 46*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 47*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 48*e65e175bSOded Gabbay #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay /* TPC0_QM_GLBL_PROT */ 51*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0 52*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1 53*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1 54*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2 55*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2 56*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4 57*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3 58*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8 59*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 60*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 61*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 62*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 63*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 64*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 65*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 66*e65e175bSOded Gabbay #define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay /* TPC0_QM_GLBL_ERR_CFG */ 69*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 70*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 71*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 72*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 73*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 74*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 75*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 76*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 77*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 78*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 79*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 80*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 81*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 82*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 83*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 84*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 85*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 86*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 87*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 88*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 89*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 90*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 91*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 92*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay /* TPC0_QM_GLBL_ERR_ADDR_LO */ 95*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 96*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay /* TPC0_QM_GLBL_ERR_ADDR_HI */ 99*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 100*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay /* TPC0_QM_GLBL_ERR_WDATA */ 103*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 104*e65e175bSOded Gabbay #define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay /* TPC0_QM_GLBL_SECURE_PROPS */ 107*e65e175bSOded Gabbay #define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 108*e65e175bSOded Gabbay #define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF 109*e65e175bSOded Gabbay #define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 110*e65e175bSOded Gabbay #define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay /* TPC0_QM_GLBL_NON_SECURE_PROPS */ 113*e65e175bSOded Gabbay #define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 114*e65e175bSOded Gabbay #define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF 115*e65e175bSOded Gabbay #define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 116*e65e175bSOded Gabbay #define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay /* TPC0_QM_GLBL_STS0 */ 119*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 120*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 121*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 122*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 123*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2 124*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4 125*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 126*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 127*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 128*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 129*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 130*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 131*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 132*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 133*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 134*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay /* TPC0_QM_GLBL_STS1 */ 137*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 138*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 139*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 140*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 141*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 142*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 143*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 144*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 145*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 146*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 147*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 148*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 149*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 150*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 151*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 152*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 153*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 154*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 155*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 156*e65e175bSOded Gabbay #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay /* TPC0_QM_PQ_BASE_LO */ 159*e65e175bSOded Gabbay #define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 160*e65e175bSOded Gabbay #define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay /* TPC0_QM_PQ_BASE_HI */ 163*e65e175bSOded Gabbay #define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 164*e65e175bSOded Gabbay #define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay /* TPC0_QM_PQ_SIZE */ 167*e65e175bSOded Gabbay #define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 168*e65e175bSOded Gabbay #define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay /* TPC0_QM_PQ_PI */ 171*e65e175bSOded Gabbay #define TPC0_QM_PQ_PI_VAL_SHIFT 0 172*e65e175bSOded Gabbay #define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF 173*e65e175bSOded Gabbay 174*e65e175bSOded Gabbay /* TPC0_QM_PQ_CI */ 175*e65e175bSOded Gabbay #define TPC0_QM_PQ_CI_VAL_SHIFT 0 176*e65e175bSOded Gabbay #define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay /* TPC0_QM_PQ_CFG0 */ 179*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 180*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 181*e65e175bSOded Gabbay 182*e65e175bSOded Gabbay /* TPC0_QM_PQ_CFG1 */ 183*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 184*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF 185*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 186*e65e175bSOded Gabbay #define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay /* TPC0_QM_PQ_ARUSER */ 189*e65e175bSOded Gabbay #define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 190*e65e175bSOded Gabbay #define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 191*e65e175bSOded Gabbay #define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1 192*e65e175bSOded Gabbay #define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2 193*e65e175bSOded Gabbay 194*e65e175bSOded Gabbay /* TPC0_QM_PQ_PUSH0 */ 195*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0 196*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF 197*e65e175bSOded Gabbay 198*e65e175bSOded Gabbay /* TPC0_QM_PQ_PUSH1 */ 199*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0 200*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF 201*e65e175bSOded Gabbay 202*e65e175bSOded Gabbay /* TPC0_QM_PQ_PUSH2 */ 203*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0 204*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF 205*e65e175bSOded Gabbay 206*e65e175bSOded Gabbay /* TPC0_QM_PQ_PUSH3 */ 207*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0 208*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF 209*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16 210*e65e175bSOded Gabbay #define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 211*e65e175bSOded Gabbay 212*e65e175bSOded Gabbay /* TPC0_QM_PQ_STS0 */ 213*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 214*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF 215*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 216*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 217*e65e175bSOded Gabbay 218*e65e175bSOded Gabbay /* TPC0_QM_PQ_STS1 */ 219*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 220*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF 221*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 222*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 223*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 224*e65e175bSOded Gabbay #define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 225*e65e175bSOded Gabbay 226*e65e175bSOded Gabbay /* TPC0_QM_PQ_RD_RATE_LIM_EN */ 227*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 228*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 229*e65e175bSOded Gabbay 230*e65e175bSOded Gabbay /* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */ 231*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 232*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 233*e65e175bSOded Gabbay 234*e65e175bSOded Gabbay /* TPC0_QM_PQ_RD_RATE_LIM_SAT */ 235*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 236*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 237*e65e175bSOded Gabbay 238*e65e175bSOded Gabbay /* TPC0_QM_PQ_RD_RATE_LIM_TOUT */ 239*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 240*e65e175bSOded Gabbay #define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 241*e65e175bSOded Gabbay 242*e65e175bSOded Gabbay /* TPC0_QM_CQ_CFG0 */ 243*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 244*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 245*e65e175bSOded Gabbay 246*e65e175bSOded Gabbay /* TPC0_QM_CQ_CFG1 */ 247*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 248*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF 249*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 250*e65e175bSOded Gabbay #define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 251*e65e175bSOded Gabbay 252*e65e175bSOded Gabbay /* TPC0_QM_CQ_ARUSER */ 253*e65e175bSOded Gabbay #define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 254*e65e175bSOded Gabbay #define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 255*e65e175bSOded Gabbay #define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1 256*e65e175bSOded Gabbay #define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2 257*e65e175bSOded Gabbay 258*e65e175bSOded Gabbay /* TPC0_QM_CQ_PTR_LO */ 259*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0 260*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF 261*e65e175bSOded Gabbay 262*e65e175bSOded Gabbay /* TPC0_QM_CQ_PTR_HI */ 263*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0 264*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF 265*e65e175bSOded Gabbay 266*e65e175bSOded Gabbay /* TPC0_QM_CQ_TSIZE */ 267*e65e175bSOded Gabbay #define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0 268*e65e175bSOded Gabbay #define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF 269*e65e175bSOded Gabbay 270*e65e175bSOded Gabbay /* TPC0_QM_CQ_CTL */ 271*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_RPT_SHIFT 0 272*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF 273*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_CTL_SHIFT 16 274*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000 275*e65e175bSOded Gabbay 276*e65e175bSOded Gabbay /* TPC0_QM_CQ_PTR_LO_STS */ 277*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 278*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF 279*e65e175bSOded Gabbay 280*e65e175bSOded Gabbay /* TPC0_QM_CQ_PTR_HI_STS */ 281*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 282*e65e175bSOded Gabbay #define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF 283*e65e175bSOded Gabbay 284*e65e175bSOded Gabbay /* TPC0_QM_CQ_TSIZE_STS */ 285*e65e175bSOded Gabbay #define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 286*e65e175bSOded Gabbay #define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF 287*e65e175bSOded Gabbay 288*e65e175bSOded Gabbay /* TPC0_QM_CQ_CTL_STS */ 289*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 290*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF 291*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 292*e65e175bSOded Gabbay #define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 293*e65e175bSOded Gabbay 294*e65e175bSOded Gabbay /* TPC0_QM_CQ_STS0 */ 295*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 296*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF 297*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 298*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 299*e65e175bSOded Gabbay 300*e65e175bSOded Gabbay /* TPC0_QM_CQ_STS1 */ 301*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 302*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF 303*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 304*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 305*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 306*e65e175bSOded Gabbay #define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 307*e65e175bSOded Gabbay 308*e65e175bSOded Gabbay /* TPC0_QM_CQ_RD_RATE_LIM_EN */ 309*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 310*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 311*e65e175bSOded Gabbay 312*e65e175bSOded Gabbay /* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */ 313*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 314*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF 315*e65e175bSOded Gabbay 316*e65e175bSOded Gabbay /* TPC0_QM_CQ_RD_RATE_LIM_SAT */ 317*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 318*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF 319*e65e175bSOded Gabbay 320*e65e175bSOded Gabbay /* TPC0_QM_CQ_RD_RATE_LIM_TOUT */ 321*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 322*e65e175bSOded Gabbay #define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF 323*e65e175bSOded Gabbay 324*e65e175bSOded Gabbay /* TPC0_QM_CQ_IFIFO_CNT */ 325*e65e175bSOded Gabbay #define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 326*e65e175bSOded Gabbay #define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 327*e65e175bSOded Gabbay 328*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ 329*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 330*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF 331*e65e175bSOded Gabbay 332*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ 333*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 334*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF 335*e65e175bSOded Gabbay 336*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ 337*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 338*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF 339*e65e175bSOded Gabbay 340*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ 341*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 342*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF 343*e65e175bSOded Gabbay 344*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ 345*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 346*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF 347*e65e175bSOded Gabbay 348*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ 349*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 350*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF 351*e65e175bSOded Gabbay 352*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ 353*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 354*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF 355*e65e175bSOded Gabbay 356*e65e175bSOded Gabbay /* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ 357*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 358*e65e175bSOded Gabbay #define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF 359*e65e175bSOded Gabbay 360*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ 361*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 362*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF 363*e65e175bSOded Gabbay 364*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ 365*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 366*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 367*e65e175bSOded Gabbay 368*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ 369*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 370*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 371*e65e175bSOded Gabbay 372*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ 373*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 374*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF 375*e65e175bSOded Gabbay 376*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */ 377*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 378*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF 379*e65e175bSOded Gabbay 380*e65e175bSOded Gabbay /* TPC0_QM_CP_LDMA_COMMIT_OFFSET */ 381*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 382*e65e175bSOded Gabbay #define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF 383*e65e175bSOded Gabbay 384*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE0_RDATA */ 385*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 386*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF 387*e65e175bSOded Gabbay 388*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE1_RDATA */ 389*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 390*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF 391*e65e175bSOded Gabbay 392*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE2_RDATA */ 393*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 394*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF 395*e65e175bSOded Gabbay 396*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE3_RDATA */ 397*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 398*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF 399*e65e175bSOded Gabbay 400*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE0_CNT */ 401*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 402*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF 403*e65e175bSOded Gabbay 404*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE1_CNT */ 405*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 406*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF 407*e65e175bSOded Gabbay 408*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE2_CNT */ 409*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 410*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF 411*e65e175bSOded Gabbay 412*e65e175bSOded Gabbay /* TPC0_QM_CP_FENCE3_CNT */ 413*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 414*e65e175bSOded Gabbay #define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF 415*e65e175bSOded Gabbay 416*e65e175bSOded Gabbay /* TPC0_QM_CP_STS */ 417*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 418*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF 419*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_ERDY_SHIFT 16 420*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_ERDY_MASK 0x10000 421*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_RRDY_SHIFT 17 422*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_RRDY_MASK 0x20000 423*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_MRDY_SHIFT 18 424*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_MRDY_MASK 0x40000 425*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 426*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 427*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 428*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 429*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 430*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 431*e65e175bSOded Gabbay 432*e65e175bSOded Gabbay /* TPC0_QM_CP_CURRENT_INST_LO */ 433*e65e175bSOded Gabbay #define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 434*e65e175bSOded Gabbay #define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF 435*e65e175bSOded Gabbay 436*e65e175bSOded Gabbay /* TPC0_QM_CP_CURRENT_INST_HI */ 437*e65e175bSOded Gabbay #define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 438*e65e175bSOded Gabbay #define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF 439*e65e175bSOded Gabbay 440*e65e175bSOded Gabbay /* TPC0_QM_CP_BARRIER_CFG */ 441*e65e175bSOded Gabbay #define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 442*e65e175bSOded Gabbay #define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF 443*e65e175bSOded Gabbay 444*e65e175bSOded Gabbay /* TPC0_QM_CP_DBG_0 */ 445*e65e175bSOded Gabbay #define TPC0_QM_CP_DBG_0_VAL_SHIFT 0 446*e65e175bSOded Gabbay #define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF 447*e65e175bSOded Gabbay 448*e65e175bSOded Gabbay /* TPC0_QM_PQ_BUF_ADDR */ 449*e65e175bSOded Gabbay #define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0 450*e65e175bSOded Gabbay #define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 451*e65e175bSOded Gabbay 452*e65e175bSOded Gabbay /* TPC0_QM_PQ_BUF_RDATA */ 453*e65e175bSOded Gabbay #define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0 454*e65e175bSOded Gabbay #define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 455*e65e175bSOded Gabbay 456*e65e175bSOded Gabbay /* TPC0_QM_CQ_BUF_ADDR */ 457*e65e175bSOded Gabbay #define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0 458*e65e175bSOded Gabbay #define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF 459*e65e175bSOded Gabbay 460*e65e175bSOded Gabbay /* TPC0_QM_CQ_BUF_RDATA */ 461*e65e175bSOded Gabbay #define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0 462*e65e175bSOded Gabbay #define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF 463*e65e175bSOded Gabbay 464*e65e175bSOded Gabbay #endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ 465