1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0
2*e65e175bSOded Gabbay  *
3*e65e175bSOded Gabbay  * Copyright 2016-2018 HabanaLabs, Ltd.
4*e65e175bSOded Gabbay  * All Rights Reserved.
5*e65e175bSOded Gabbay  *
6*e65e175bSOded Gabbay  */
7*e65e175bSOded Gabbay 
8*e65e175bSOded Gabbay /************************************
9*e65e175bSOded Gabbay  ** This is an auto-generated file **
10*e65e175bSOded Gabbay  **       DO NOT EDIT BELOW        **
11*e65e175bSOded Gabbay  ************************************/
12*e65e175bSOded Gabbay 
13*e65e175bSOded Gabbay #ifndef ASIC_REG_MMU_REGS_H_
14*e65e175bSOded Gabbay #define ASIC_REG_MMU_REGS_H_
15*e65e175bSOded Gabbay 
16*e65e175bSOded Gabbay /*
17*e65e175bSOded Gabbay  *****************************************
18*e65e175bSOded Gabbay  *   MMU (Prototype: MMU)
19*e65e175bSOded Gabbay  *****************************************
20*e65e175bSOded Gabbay  */
21*e65e175bSOded Gabbay 
22*e65e175bSOded Gabbay #define mmMMU_INPUT_FIFO_THRESHOLD                                   0x480000
23*e65e175bSOded Gabbay 
24*e65e175bSOded Gabbay #define mmMMU_MMU_ENABLE                                             0x48000C
25*e65e175bSOded Gabbay 
26*e65e175bSOded Gabbay #define mmMMU_FORCE_ORDERING                                         0x480010
27*e65e175bSOded Gabbay 
28*e65e175bSOded Gabbay #define mmMMU_FEATURE_ENABLE                                         0x480014
29*e65e175bSOded Gabbay 
30*e65e175bSOded Gabbay #define mmMMU_VA_ORDERING_MASK_31_7                                  0x480018
31*e65e175bSOded Gabbay 
32*e65e175bSOded Gabbay #define mmMMU_VA_ORDERING_MASK_49_32                                 0x48001C
33*e65e175bSOded Gabbay 
34*e65e175bSOded Gabbay #define mmMMU_LOG2_DDR_SIZE                                          0x480020
35*e65e175bSOded Gabbay 
36*e65e175bSOded Gabbay #define mmMMU_SCRAMBLER                                              0x480024
37*e65e175bSOded Gabbay 
38*e65e175bSOded Gabbay #define mmMMU_MEM_INIT_BUSY                                          0x480028
39*e65e175bSOded Gabbay 
40*e65e175bSOded Gabbay #define mmMMU_SPI_MASK                                               0x48002C
41*e65e175bSOded Gabbay 
42*e65e175bSOded Gabbay #define mmMMU_SPI_CAUSE                                              0x480030
43*e65e175bSOded Gabbay 
44*e65e175bSOded Gabbay #define mmMMU_PAGE_ERROR_CAPTURE                                     0x480034
45*e65e175bSOded Gabbay 
46*e65e175bSOded Gabbay #define mmMMU_PAGE_ERROR_CAPTURE_VA                                  0x480038
47*e65e175bSOded Gabbay 
48*e65e175bSOded Gabbay #define mmMMU_ACCESS_ERROR_CAPTURE                                   0x48003C
49*e65e175bSOded Gabbay 
50*e65e175bSOded Gabbay #define mmMMU_ACCESS_ERROR_CAPTURE_VA                                0x480040
51*e65e175bSOded Gabbay 
52*e65e175bSOded Gabbay #endif /* ASIC_REG_MMU_REGS_H_ */
53