1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA_CH_2_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA_CH_2_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA_CH_2 (Prototype: DMA_CH) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmDMA_CH_2_CFG0 0x411000 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmDMA_CH_2_CFG1 0x411004 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmDMA_CH_2_ERRMSG_ADDR_LO 0x411008 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmDMA_CH_2_ERRMSG_ADDR_HI 0x41100C 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmDMA_CH_2_ERRMSG_WDATA 0x411010 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_COMP_ADDR_LO 0x411014 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_COMP_ADDR_HI 0x411018 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_COMP_WDATA 0x41101C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_COMP_ADDR_LO 0x411020 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_COMP_ADDR_HI 0x411024 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_COMP_WDATA 0x411028 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmDMA_CH_2_LDMA_SRC_ADDR_LO 0x41102C 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmDMA_CH_2_LDMA_SRC_ADDR_HI 0x411030 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmDMA_CH_2_LDMA_DST_ADDR_LO 0x411034 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmDMA_CH_2_LDMA_DST_ADDR_HI 0x411038 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmDMA_CH_2_LDMA_TSIZE 0x41103C 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmDMA_CH_2_COMIT_TRANSFER 0x411040 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmDMA_CH_2_STS0 0x411044 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmDMA_CH_2_STS1 0x411048 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmDMA_CH_2_STS2 0x41104C 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmDMA_CH_2_STS3 0x411050 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmDMA_CH_2_STS4 0x411054 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmDMA_CH_2_SRC_ADDR_LO_STS 0x411058 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmDMA_CH_2_SRC_ADDR_HI_STS 0x41105C 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmDMA_CH_2_SRC_TSIZE_STS 0x411060 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmDMA_CH_2_DST_ADDR_LO_STS 0x411064 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmDMA_CH_2_DST_ADDR_HI_STS 0x411068 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmDMA_CH_2_DST_TSIZE_STS 0x41106C 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_RATE_LIM_EN 0x411070 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_RATE_LIM_RST_TOKEN 0x411074 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_RATE_LIM_SAT 0x411078 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmDMA_CH_2_RD_RATE_LIM_TOUT 0x41107C 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_RATE_LIM_EN 0x411080 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_RATE_LIM_RST_TOKEN 0x411084 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_RATE_LIM_SAT 0x411088 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmDMA_CH_2_WR_RATE_LIM_TOUT 0x41108C 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmDMA_CH_2_CFG2 0x411090 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_CTL 0x411100 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_LO 0x411104 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_HI 0x411108 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_0 0x41110C 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_0 0x411110 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_0 0x411114 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_0 0x411118 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_STRIDE_0 0x41111C 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_1 0x411120 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_1 0x411124 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_1 0x411128 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_1 0x41112C 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_STRIDE_1 0x411130 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_2 0x411134 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_2 0x411138 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_2 0x41113C 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_2 0x411140 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_STRIDE_2 0x411144 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_3 0x411148 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_3 0x41114C 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_3 0x411150 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_3 0x411154 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_STRIDE_3 0x411158 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_4 0x41115C 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_4 0x411160 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_4 0x411164 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_4 0x411168 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_SRC_STRIDE_4 0x41116C 151*e65e175bSOded Gabbay 152*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_BASE_ADDR_LO 0x411170 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_BASE_ADDR_HI 0x411174 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_BASE_0 0x411178 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_0 0x41117C 159*e65e175bSOded Gabbay 160*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_0 0x411180 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_START_OFFSET_0 0x411184 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_STRIDE_0 0x411188 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_BASE_1 0x41118C 167*e65e175bSOded Gabbay 168*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_1 0x411190 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_1 0x411194 171*e65e175bSOded Gabbay 172*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_START_OFFSET_1 0x411198 173*e65e175bSOded Gabbay 174*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_STRIDE_1 0x41119C 175*e65e175bSOded Gabbay 176*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_BASE_2 0x4111A0 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_2 0x4111A4 179*e65e175bSOded Gabbay 180*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_2 0x4111A8 181*e65e175bSOded Gabbay 182*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_START_OFFSET_2 0x4111AC 183*e65e175bSOded Gabbay 184*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_STRIDE_2 0x4111B0 185*e65e175bSOded Gabbay 186*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_BASE_3 0x4111B4 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_3 0x4111B8 189*e65e175bSOded Gabbay 190*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_3 0x4111BC 191*e65e175bSOded Gabbay 192*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_START_OFFSET_3 0x4111C0 193*e65e175bSOded Gabbay 194*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_STRIDE_3 0x4111C4 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_BASE_4 0x4111C8 197*e65e175bSOded Gabbay 198*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_4 0x4111CC 199*e65e175bSOded Gabbay 200*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_4 0x4111D0 201*e65e175bSOded Gabbay 202*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_START_OFFSET_4 0x4111D4 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay #define mmDMA_CH_2_TDMA_DST_STRIDE_4 0x4111D8 205*e65e175bSOded Gabbay 206*e65e175bSOded Gabbay #define mmDMA_CH_2_MEM_INIT_BUSY 0x4111FC 207*e65e175bSOded Gabbay 208*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA_CH_2_REGS_H_ */ 209