1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA_CH_1_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA_CH_1_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA_CH_1 (Prototype: DMA_CH) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmDMA_CH_1_CFG0 0x409000 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmDMA_CH_1_CFG1 0x409004 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmDMA_CH_1_ERRMSG_ADDR_LO 0x409008 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmDMA_CH_1_ERRMSG_ADDR_HI 0x40900C 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmDMA_CH_1_ERRMSG_WDATA 0x409010 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_COMP_ADDR_LO 0x409014 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_COMP_ADDR_HI 0x409018 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_COMP_WDATA 0x40901C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_COMP_ADDR_LO 0x409020 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_COMP_ADDR_HI 0x409024 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_COMP_WDATA 0x409028 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmDMA_CH_1_LDMA_SRC_ADDR_LO 0x40902C 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmDMA_CH_1_LDMA_SRC_ADDR_HI 0x409030 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmDMA_CH_1_LDMA_DST_ADDR_LO 0x409034 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmDMA_CH_1_LDMA_DST_ADDR_HI 0x409038 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmDMA_CH_1_LDMA_TSIZE 0x40903C 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmDMA_CH_1_COMIT_TRANSFER 0x409040 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmDMA_CH_1_STS0 0x409044 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmDMA_CH_1_STS1 0x409048 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmDMA_CH_1_STS2 0x40904C 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmDMA_CH_1_STS3 0x409050 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmDMA_CH_1_STS4 0x409054 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmDMA_CH_1_SRC_ADDR_LO_STS 0x409058 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmDMA_CH_1_SRC_ADDR_HI_STS 0x40905C 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmDMA_CH_1_SRC_TSIZE_STS 0x409060 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmDMA_CH_1_DST_ADDR_LO_STS 0x409064 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmDMA_CH_1_DST_ADDR_HI_STS 0x409068 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmDMA_CH_1_DST_TSIZE_STS 0x40906C 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_RATE_LIM_EN 0x409070 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN 0x409074 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_RATE_LIM_SAT 0x409078 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmDMA_CH_1_RD_RATE_LIM_TOUT 0x40907C 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_RATE_LIM_EN 0x409080 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN 0x409084 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_RATE_LIM_SAT 0x409088 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmDMA_CH_1_WR_RATE_LIM_TOUT 0x40908C 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmDMA_CH_1_CFG2 0x409090 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_CTL 0x409100 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO 0x409104 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI 0x409108 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0 0x40910C 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_0 0x409110 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_0 0x409114 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_0 0x409118 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_STRIDE_0 0x40911C 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_1 0x409120 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_1 0x409124 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_1 0x409128 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_1 0x40912C 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_STRIDE_1 0x409130 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_2 0x409134 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_2 0x409138 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_2 0x40913C 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_2 0x409140 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_STRIDE_2 0x409144 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_3 0x409148 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_3 0x40914C 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_3 0x409150 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_3 0x409154 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_STRIDE_3 0x409158 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_BASE_4 0x40915C 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_4 0x409160 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_4 0x409164 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_START_OFFSET_4 0x409168 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_SRC_STRIDE_4 0x40916C 151*e65e175bSOded Gabbay 152*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_BASE_ADDR_LO 0x409170 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_BASE_ADDR_HI 0x409174 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_BASE_0 0x409178 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_0 0x40917C 159*e65e175bSOded Gabbay 160*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_0 0x409180 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_START_OFFSET_0 0x409184 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_STRIDE_0 0x409188 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_BASE_1 0x40918C 167*e65e175bSOded Gabbay 168*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_1 0x409190 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_1 0x409194 171*e65e175bSOded Gabbay 172*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_START_OFFSET_1 0x409198 173*e65e175bSOded Gabbay 174*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_STRIDE_1 0x40919C 175*e65e175bSOded Gabbay 176*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_BASE_2 0x4091A0 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_2 0x4091A4 179*e65e175bSOded Gabbay 180*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_2 0x4091A8 181*e65e175bSOded Gabbay 182*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_START_OFFSET_2 0x4091AC 183*e65e175bSOded Gabbay 184*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_STRIDE_2 0x4091B0 185*e65e175bSOded Gabbay 186*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_BASE_3 0x4091B4 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_3 0x4091B8 189*e65e175bSOded Gabbay 190*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_3 0x4091BC 191*e65e175bSOded Gabbay 192*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_START_OFFSET_3 0x4091C0 193*e65e175bSOded Gabbay 194*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_STRIDE_3 0x4091C4 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_BASE_4 0x4091C8 197*e65e175bSOded Gabbay 198*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_ROI_SIZE_4 0x4091CC 199*e65e175bSOded Gabbay 200*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_4 0x4091D0 201*e65e175bSOded Gabbay 202*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_START_OFFSET_4 0x4091D4 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay #define mmDMA_CH_1_TDMA_DST_STRIDE_4 0x4091D8 205*e65e175bSOded Gabbay 206*e65e175bSOded Gabbay #define mmDMA_CH_1_MEM_INIT_BUSY 0x4091FC 207*e65e175bSOded Gabbay 208*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA_CH_1_REGS_H_ */ 209