1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_XBAR_EDGE_0_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * XBAR_EDGE_0 19*e65e175bSOded Gabbay * (Prototype: XBAR) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_LBW_INTERNAL_ADDR_RGF 0x4D480D0 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DBG_INTERNAL_ADDR_FUN 0x4D480D4 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_EMEM_HBM_BIT_LOCATION 0x4D48100 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_EMEM_PC_BIT_LOCATION 0x4D48104 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_HIF_WR_RS_CH_LOCATION 0x4D48108 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_HBW_MST_ARB_WEIGHT 0x4D4810C 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_0 0x4D48110 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_PC_IDX_MAP_1 0x4D48114 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_RD_LL_ARB_0 0x4D48120 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_RD_LL_ARB_1 0x4D48124 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_WR_LL_ARB_0 0x4D48128 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_MMU_WR_LL_ARB_1 0x4D4812C 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_0 0x4D48130 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_HBM_USER_RESP_OVR_1 0x4D48134 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_0 0x4D48140 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_1 0x4D48144 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_2 0x4D48148 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_3 0x4D4814C 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_4 0x4D48150 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_5 0x4D48154 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_6 0x4D48158 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_7 0x4D4815C 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_8 0x4D48160 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_9 0x4D48164 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_10 0x4D48168 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_RD_11 0x4D4816C 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_0 0x4D48180 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_1 0x4D48184 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_2 0x4D48188 160*e65e175bSOded Gabbay 161*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_3 0x4D4818C 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_4 0x4D48190 164*e65e175bSOded Gabbay 165*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_5 0x4D48194 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_6 0x4D48198 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_7 0x4D4819C 170*e65e175bSOded Gabbay 171*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_8 0x4D481A0 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_9 0x4D481A4 174*e65e175bSOded Gabbay 175*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_10 0x4D481A8 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_RL_WR_11 0x4D481AC 178*e65e175bSOded Gabbay 179*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_E2E_CRDT_SLV_0 0x4D481B0 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_E2E_CRDT_SLV_1 0x4D481B4 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_E2E_CRDT_SLV_2 0x4D481B8 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_E2E_CRDT_DEBUG 0x4D481BC 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_UPSCALE 0x4D481C0 188*e65e175bSOded Gabbay 189*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DOWN_CONV 0x4D481C4 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN 0x4D481D0 192*e65e175bSOded Gabbay 193*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD 0x4D481D4 194*e65e175bSOded Gabbay 195*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE 0x4D481D8 196*e65e175bSOded Gabbay 197*e65e175bSOded Gabbay #define mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY 0x4D481DC 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay #endif /* ASIC_REG_XBAR_EDGE_0_REGS_H_ */ 200