1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PDMA0_CORE_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PDMA0_CORE_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PDMA0_CORE 19*e65e175bSOded Gabbay * (Prototype: DMA_CORE) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmPDMA0_CORE_CFG_0 0x4C8B000 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmPDMA0_CORE_CFG_1 0x4C8B004 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmPDMA0_CORE_PROT 0x4C8B008 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmPDMA0_CORE_CKG 0x4C8B00C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_GLBL 0x4C8B07C 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmPDMA0_CORE_ERR_CFG 0x4C8B300 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS0 0x4C8B380 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS1 0x4C8B384 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmPDMA0_CORE_PWRLP_STS 0x4C8B704 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_STS 0x4C8B714 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */ 158