1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_PDMA0_CORE_CTX_REGS_H_
14 #define ASIC_REG_PDMA0_CORE_CTX_REGS_H_
15 
16 /*
17  *****************************************
18  *   PDMA0_CORE_CTX
19  *   (Prototype: DMA_CORE_CTX)
20  *****************************************
21  */
22 
23 #define mmPDMA0_CORE_CTX_RATE_LIM_TKN 0x4C8B860
24 
25 #define mmPDMA0_CORE_CTX_PWRLP 0x4C8B864
26 
27 #define mmPDMA0_CORE_CTX_TE_NUMROWS 0x4C8B868
28 
29 #define mmPDMA0_CORE_CTX_IDX 0x4C8B86C
30 
31 #define mmPDMA0_CORE_CTX_IDX_INC 0x4C8B870
32 
33 #define mmPDMA0_CORE_CTX_CTRL 0x4C8B874
34 
35 #define mmPDMA0_CORE_CTX_SRC_TSIZE_0 0x4C8B878
36 
37 #define mmPDMA0_CORE_CTX_SRC_TSIZE_1 0x4C8B87C
38 
39 #define mmPDMA0_CORE_CTX_SRC_STRIDE_1 0x4C8B880
40 
41 #define mmPDMA0_CORE_CTX_SRC_TSIZE_2 0x4C8B884
42 
43 #define mmPDMA0_CORE_CTX_SRC_STRIDE_2 0x4C8B888
44 
45 #define mmPDMA0_CORE_CTX_SRC_TSIZE_3 0x4C8B88C
46 
47 #define mmPDMA0_CORE_CTX_SRC_STRIDE_3 0x4C8B890
48 
49 #define mmPDMA0_CORE_CTX_SRC_TSIZE_4 0x4C8B894
50 
51 #define mmPDMA0_CORE_CTX_SRC_STRIDE_4 0x4C8B898
52 
53 #define mmPDMA0_CORE_CTX_DST_TSIZE_1 0x4C8B89C
54 
55 #define mmPDMA0_CORE_CTX_DST_STRIDE_1 0x4C8B8A0
56 
57 #define mmPDMA0_CORE_CTX_DST_TSIZE_2 0x4C8B8A4
58 
59 #define mmPDMA0_CORE_CTX_DST_STRIDE_2 0x4C8B8A8
60 
61 #define mmPDMA0_CORE_CTX_DST_TSIZE_3 0x4C8B8AC
62 
63 #define mmPDMA0_CORE_CTX_DST_STRIDE_3 0x4C8B8B0
64 
65 #define mmPDMA0_CORE_CTX_DST_TSIZE_4 0x4C8B8B4
66 
67 #define mmPDMA0_CORE_CTX_DST_STRIDE_4 0x4C8B8B8
68 
69 #define mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x4C8B8BC
70 
71 #define mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x4C8B8C0
72 
73 #define mmPDMA0_CORE_CTX_WR_COMP_WDATA 0x4C8B8C4
74 
75 #define mmPDMA0_CORE_CTX_SRC_OFFSET_LO 0x4C8B8C8
76 
77 #define mmPDMA0_CORE_CTX_SRC_OFFSET_HI 0x4C8B8CC
78 
79 #define mmPDMA0_CORE_CTX_DST_OFFSET_LO 0x4C8B8D0
80 
81 #define mmPDMA0_CORE_CTX_DST_OFFSET_HI 0x4C8B8D4
82 
83 #define mmPDMA0_CORE_CTX_SRC_BASE_LO 0x4C8B8D8
84 
85 #define mmPDMA0_CORE_CTX_SRC_BASE_HI 0x4C8B8DC
86 
87 #define mmPDMA0_CORE_CTX_DST_BASE_LO 0x4C8B8E0
88 
89 #define mmPDMA0_CORE_CTX_DST_BASE_HI 0x4C8B8E4
90 
91 #define mmPDMA0_CORE_CTX_DST_TSIZE_0 0x4C8B8E8
92 
93 #define mmPDMA0_CORE_CTX_COMMIT 0x4C8B8EC
94 
95 #endif /* ASIC_REG_PDMA0_CORE_CTX_REGS_H_ */
96