1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PCIE_WRAP_SPECIAL 19*e65e175bSOded Gabbay * (Prototype: SPECIAL_REGS) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_ADDR 0x4C01F24 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_MEM_RM 0x4C01F28 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_MASK 0x4C01F40 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_ADDR 0x4C01F44 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_ERR_CAUSE 0x4C01F48 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0 0x4C01F60 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_1 0x4C01F64 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_2 0x4C01F68 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SPARE_3 0x4C01F6C 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_0 0x4C01F80 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_1 0x4C01F84 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_2 0x4C01F88 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_3 0x4C01F8C 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_4 0x4C01F90 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_5 0x4C01F94 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_6 0x4C01F98 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_7 0x4C01F9C 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_8 0x4C01FA0 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_9 0x4C01FA4 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_10 0x4C01FA8 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_11 0x4C01FAC 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_12 0x4C01FB0 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_13 0x4C01FB4 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_14 0x4C01FB8 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_15 0x4C01FBC 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_16 0x4C01FC0 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_17 0x4C01FC4 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_18 0x4C01FC8 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_19 0x4C01FCC 160*e65e175bSOded Gabbay 161*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_20 0x4C01FD0 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_21 0x4C01FD4 164*e65e175bSOded Gabbay 165*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_22 0x4C01FD8 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_23 0x4C01FDC 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_24 0x4C01FE0 170*e65e175bSOded Gabbay 171*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_25 0x4C01FE4 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_26 0x4C01FE8 174*e65e175bSOded Gabbay 175*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_27 0x4C01FEC 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_28 0x4C01FF0 178*e65e175bSOded Gabbay 179*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_29 0x4C01FF4 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_30 0x4C01FF8 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define mmPCIE_WRAP_SPECIAL_GLBL_SEC_31 0x4C01FFC 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #endif /* ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_ */ 186