1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_
14 #define ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_
15 
16 /*
17  *****************************************
18  *   PCIE_VDEC0_CTRL_SPECIAL
19  *   (Prototype: SPECIAL_REGS)
20  *****************************************
21  */
22 
23 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x4F04E80
24 
25 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x4F04E84
26 
27 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x4F04E88
28 
29 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x4F04E8C
30 
31 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x4F04E90
32 
33 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x4F04E94
34 
35 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x4F04E98
36 
37 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x4F04E9C
38 
39 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x4F04EA0
40 
41 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x4F04EA4
42 
43 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x4F04EA8
44 
45 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x4F04EAC
46 
47 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x4F04EB0
48 
49 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x4F04EB4
50 
51 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x4F04EB8
52 
53 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x4F04EBC
54 
55 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x4F04EC0
56 
57 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x4F04EC4
58 
59 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x4F04EC8
60 
61 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x4F04ECC
62 
63 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x4F04ED0
64 
65 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x4F04ED4
66 
67 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x4F04ED8
68 
69 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x4F04EDC
70 
71 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x4F04EE0
72 
73 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x4F04EE4
74 
75 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x4F04EE8
76 
77 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x4F04EEC
78 
79 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x4F04EF0
80 
81 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x4F04EF4
82 
83 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x4F04EF8
84 
85 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x4F04EFC
86 
87 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x4F04F00
88 
89 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x4F04F04
90 
91 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x4F04F0C
92 
93 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x4F04F10
94 
95 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x4F04F14
96 
97 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x4F04F18
98 
99 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4F04F1C
100 
101 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x4F04F20
102 
103 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_ADDR 0x4F04F24
104 
105 #define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_RM 0x4F04F28
106 
107 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_MASK 0x4F04F40
108 
109 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_ADDR 0x4F04F44
110 
111 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_ERR_CAUSE 0x4F04F48
112 
113 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_0 0x4F04F60
114 
115 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_1 0x4F04F64
116 
117 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_2 0x4F04F68
118 
119 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SPARE_3 0x4F04F6C
120 
121 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_0 0x4F04F80
122 
123 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_1 0x4F04F84
124 
125 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_2 0x4F04F88
126 
127 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_3 0x4F04F8C
128 
129 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_4 0x4F04F90
130 
131 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_5 0x4F04F94
132 
133 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_6 0x4F04F98
134 
135 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_7 0x4F04F9C
136 
137 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_8 0x4F04FA0
138 
139 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_9 0x4F04FA4
140 
141 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_10 0x4F04FA8
142 
143 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_11 0x4F04FAC
144 
145 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_12 0x4F04FB0
146 
147 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_13 0x4F04FB4
148 
149 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_14 0x4F04FB8
150 
151 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_15 0x4F04FBC
152 
153 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_16 0x4F04FC0
154 
155 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_17 0x4F04FC4
156 
157 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_18 0x4F04FC8
158 
159 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_19 0x4F04FCC
160 
161 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_20 0x4F04FD0
162 
163 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_21 0x4F04FD4
164 
165 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_22 0x4F04FD8
166 
167 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_23 0x4F04FDC
168 
169 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_24 0x4F04FE0
170 
171 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_25 0x4F04FE4
172 
173 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_26 0x4F04FE8
174 
175 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_27 0x4F04FEC
176 
177 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_28 0x4F04FF0
178 
179 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_29 0x4F04FF4
180 
181 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_30 0x4F04FF8
182 
183 #define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_SEC_31 0x4F04FFC
184 
185 #endif /* ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_ */
186