1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PCIE_VDEC0_BRDG_CTRL 19*e65e175bSOded Gabbay * (Prototype: VDEC_BRDG_CTRL) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_CGM_DISABLE 0x4F03100 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_IDLE_MASK 0x4F03104 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x4F03108 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x4F0310C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL 0x4F03110 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x4F03114 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR 0x4F03120 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x4F03124 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x4F03128 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x4F0312C 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x4F03130 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x4F03134 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x4F03138 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x4F03160 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x4F03170 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x4F03180 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x4F03190 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x4F031A0 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x4F031A4 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x4F031B0 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x4F031B4 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x4F031C0 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x4F031C4 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x4F031D0 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x4F03200 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x4F03230 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x4F03260 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x4F03270 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x4F03280 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x4F03290 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x4F03294 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x4F032A0 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x4F032A4 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x4F032B0 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x4F032B4 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x4F032C0 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x4F032C4 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x4F032D0 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x4F03300 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x4F03310 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x4F03320 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x4F03330 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x4F03334 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x4F03338 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x4F03340 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x4F03350 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x4F03360 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x4F03380 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x4F03390 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x4F03394 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x4F033C0 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x4F033D0 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x4F033E0 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x4F03400 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x4F03410 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x4F03420 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x4F03430 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x4F03434 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x4F03438 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x4F03440 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x4F03450 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x4F03460 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x4F03480 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x4F03490 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x4F03494 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x4F034C0 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x4F034D0 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x4F034E0 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x4F03500 160*e65e175bSOded Gabbay 161*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x4F03510 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x4F03520 164*e65e175bSOded Gabbay 165*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x4F03530 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x4F03534 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x4F03538 170*e65e175bSOded Gabbay 171*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x4F03540 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x4F03550 174*e65e175bSOded Gabbay 175*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x4F03560 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x4F03580 178*e65e175bSOded Gabbay 179*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x4F03590 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x4F03594 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x4F035C0 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x4F035D0 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x4F035E0 188*e65e175bSOded Gabbay 189*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x4F03600 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x4F03610 192*e65e175bSOded Gabbay 193*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x4F03620 194*e65e175bSOded Gabbay 195*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x4F03630 196*e65e175bSOded Gabbay 197*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x4F03634 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x4F03638 200*e65e175bSOded Gabbay 201*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x4F03640 202*e65e175bSOded Gabbay 203*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x4F03650 204*e65e175bSOded Gabbay 205*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x4F03660 206*e65e175bSOded Gabbay 207*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x4F03680 208*e65e175bSOded Gabbay 209*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x4F03690 210*e65e175bSOded Gabbay 211*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x4F03694 212*e65e175bSOded Gabbay 213*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x4F036C0 214*e65e175bSOded Gabbay 215*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x4F036D0 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x4F036E0 218*e65e175bSOded Gabbay 219*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x4F03700 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x4F03704 222*e65e175bSOded Gabbay 223*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x4F03708 224*e65e175bSOded Gabbay 225*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x4F0370C 226*e65e175bSOded Gabbay 227*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x4F03714 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x4F03718 230*e65e175bSOded Gabbay 231*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x4F0371C 232*e65e175bSOded Gabbay 233*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x4F03720 234*e65e175bSOded Gabbay 235*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x4F03724 236*e65e175bSOded Gabbay 237*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x4F03728 238*e65e175bSOded Gabbay 239*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x4F0372C 240*e65e175bSOded Gabbay 241*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x4F03730 242*e65e175bSOded Gabbay 243*e65e175bSOded Gabbay #define mmPCIE_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x4F03734 244*e65e175bSOded Gabbay 245*e65e175bSOded Gabbay #endif /* ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_ */ 246