1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PCIE_DEC0_CMD_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PCIE_DEC0_CMD 19*e65e175bSOded Gabbay * (Prototype: VSI_CMD) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG0 0x4F00000 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG1 0x4F00004 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG2 0x4F00008 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG4 0x4F00010 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG5 0x4F00014 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG6 0x4F00018 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG8 0x4F00020 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG9 0x4F00024 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG10 0x4F00028 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG12 0x4F00030 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG13 0x4F00034 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG14 0x4F00038 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG16 0x4F00040 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG17 0x4F00044 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG18 0x4F00048 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG20 0x4F00050 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG21 0x4F00054 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG22 0x4F00058 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG24 0x4F00060 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG25 0x4F00064 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG26 0x4F00068 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG64 0x4F00100 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG65 0x4F00104 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG66 0x4F00108 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */ 86