1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PCIE_DEC0_CMD 19*e65e175bSOded Gabbay * (Prototype: VSI_CMD) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG0 */ 24*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0 25*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF 26*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16 27*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG1 */ 30*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0 31*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG2 */ 34*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0 35*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF 36*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16 37*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG3 */ 40*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0 41*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG4 */ 44*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0 45*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG5 */ 48*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0 49*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG6 */ 52*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0 53*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG7 */ 56*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0 57*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG8 */ 60*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0 61*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG9 */ 64*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0 65*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG10 */ 68*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0 69*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG11 */ 72*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0 73*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG12 */ 76*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0 77*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG13 */ 80*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0 81*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG14 */ 84*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0 85*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG15 */ 88*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0 89*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7 90*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_RSV_SHIFT 3 91*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8 92*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22 93*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000 94*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23 95*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000 96*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24 97*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000 98*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25 99*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000 100*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26 101*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000 102*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27 103*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK 0x8000000 104*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT 28 105*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK 0x10000000 106*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT 29 107*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK 0x20000000 108*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT 30 109*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK 0x40000000 110*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT 31 111*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK 0x80000000 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG16 */ 114*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT 0 115*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK 0x1 116*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT 1 117*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK 0x2 118*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT 2 119*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK 0x4 120*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT 3 121*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK 0x8 122*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT 4 123*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK 0x10 124*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT 5 125*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK 0x20 126*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT 6 127*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK 0x40 128*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_RSV_SHIFT 7 129*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG16_RSV_MASK 0xFFFFFF80 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG17 */ 132*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT 0 133*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK 0x1 134*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT 1 135*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK 0x2 136*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT 2 137*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK 0x4 138*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT 3 139*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK 0x8 140*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT 4 141*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK 0x10 142*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_RSV_1_SHIFT 5 143*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_RSV_1_MASK 0x20 144*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT 6 145*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK 0x40 146*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_RSV_SHIFT 7 147*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG17_RSV_MASK 0xFFFFFF80 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG18 */ 150*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT 0 151*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK 0x1 152*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT 1 153*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK 0x2 154*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT 2 155*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK 0x4 156*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT 3 157*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK 0x8 158*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT 4 159*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK 0x10 160*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_RSV_1_SHIFT 5 161*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_RSV_1_MASK 0x20 162*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT 6 163*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK 0x40 164*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_RSV_SHIFT 7 165*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG18_RSV_MASK 0xFFFFFF80 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG19 */ 168*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT 0 169*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK 0x7FFFFFFF 170*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT 31 171*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK 0x80000000 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG20 */ 174*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT 0 175*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK 0xFFFFFFFF 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG21 */ 178*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT 0 179*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK 0xFFFFFFFF 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG22 */ 182*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT 0 183*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK 0xFFFF 184*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG22_RSV_SHIFT 16 185*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG22_RSV_MASK 0xFFFF0000 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG23 */ 188*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT 0 189*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK 0xFF 190*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT 8 191*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK 0xFF00 192*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT 16 193*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK 0xFF0000 194*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_RSV_SHIFT 24 195*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_RSV_MASK 0xF000000 196*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT 28 197*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK 0xF0000000 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG24 */ 200*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT 0 201*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK 0xFFFFFFFF 202*e65e175bSOded Gabbay 203*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG25 */ 204*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT 0 205*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK 0xFFFF 206*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT 16 207*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK 0xFFFF0000 208*e65e175bSOded Gabbay 209*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG26 */ 210*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT 0 211*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK 0xFFFFFFFF 212*e65e175bSOded Gabbay 213*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG64 */ 214*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT 0 215*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG64_SW_DUMMY0_MASK 0xFFFFFFFF 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG65 */ 218*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT 0 219*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG65_SW_DUMMY1_MASK 0xFFFFFFFF 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG66 */ 222*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT 0 223*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG66_SW_DUMMY2_MASK 0xFFFFFFFF 224*e65e175bSOded Gabbay 225*e65e175bSOded Gabbay /* PCIE_DEC0_CMD_SWREG67 */ 226*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT 0 227*e65e175bSOded Gabbay #define PCIE_DEC0_CMD_SWREG67_SW_DUMMY3_MASK 0xFFFFFFFF 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay #endif /* ASIC_REG_PCIE_DEC0_CMD_MASKS_H_ */ 230