1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2020-2022 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 #ifndef ASIC_REG_GAUDI2_REGS_H_
9 #define ASIC_REG_GAUDI2_REGS_H_
10 
11 #include "gaudi2_blocks_linux_driver.h"
12 #include "psoc_reset_conf_regs.h"
13 #include "psoc_global_conf_regs.h"
14 #include "cpu_if_regs.h"
15 #include "pcie_aux_regs.h"
16 #include "pcie_dbi_regs.h"
17 #include "pcie_wrap_regs.h"
18 #include "pmmu_hbw_stlb_regs.h"
19 #include "psoc_timestamp_regs.h"
20 #include "psoc_etr_regs.h"
21 #include "xbar_edge_0_regs.h"
22 #include "xbar_mid_0_regs.h"
23 #include "arc_farm_kdma_regs.h"
24 #include "arc_farm_kdma_ctx_regs.h"
25 #include "arc_farm_kdma_kdma_cgm_regs.h"
26 #include "arc_farm_arc0_aux_regs.h"
27 #include "arc_farm_arc0_acp_eng_regs.h"
28 #include "arc_farm_kdma_ctx_axuser_regs.h"
29 #include "arc_farm_arc0_dup_eng_axuser_regs.h"
30 #include "arc_farm_arc0_dup_eng_regs.h"
31 #include "dcore0_sync_mngr_objs_regs.h"
32 #include "dcore0_sync_mngr_glbl_regs.h"
33 #include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
34 #include "dcore1_sync_mngr_glbl_regs.h"
35 #include "pdma0_qm_arc_aux_regs.h"
36 #include "pdma0_core_ctx_regs.h"
37 #include "pdma0_core_regs.h"
38 #include "pdma0_qm_axuser_secured_regs.h"
39 #include "pdma0_qm_regs.h"
40 #include "pdma0_qm_cgm_regs.h"
41 #include "pdma0_core_ctx_axuser_regs.h"
42 #include "pdma1_core_ctx_axuser_regs.h"
43 #include "pdma0_qm_axuser_nonsecured_regs.h"
44 #include "pdma1_qm_axuser_nonsecured_regs.h"
45 #include "dcore0_tpc0_qm_regs.h"
46 #include "dcore0_tpc0_qm_cgm_regs.h"
47 #include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
48 #include "dcore0_tpc0_qm_arc_aux_regs.h"
49 #include "dcore0_tpc0_cfg_regs.h"
50 #include "dcore0_tpc0_cfg_qm_regs.h"
51 #include "dcore0_tpc0_cfg_axuser_regs.h"
52 #include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
53 #include "dcore0_tpc0_cfg_kernel_regs.h"
54 #include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
55 #include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
56 #include "dcore0_tpc0_cfg_special_regs.h"
57 #include "dcore0_tpc0_eml_funnel_regs.h"
58 #include "dcore0_tpc0_eml_etf_regs.h"
59 #include "dcore0_tpc0_eml_stm_regs.h"
60 #include "dcore0_tpc0_eml_busmon_0_regs.h"
61 #include "dcore0_tpc0_eml_spmu_regs.h"
62 #include "pmmu_pif_regs.h"
63 #include "dcore0_edma0_qm_cgm_regs.h"
64 #include "dcore0_edma0_core_regs.h"
65 #include "dcore0_edma0_qm_regs.h"
66 #include "dcore0_edma0_qm_arc_aux_regs.h"
67 #include "dcore0_edma0_core_ctx_regs.h"
68 #include "dcore0_edma0_core_ctx_axuser_regs.h"
69 #include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
70 #include "dcore0_edma1_core_ctx_axuser_regs.h"
71 #include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
72 #include "dcore0_hmmu0_stlb_regs.h"
73 #include "dcore0_hmmu0_mmu_regs.h"
74 #include "rot0_qm_regs.h"
75 #include "rot0_qm_cgm_regs.h"
76 #include "rot0_qm_arc_aux_regs.h"
77 #include "rot0_regs.h"
78 #include "rot0_desc_regs.h"
79 #include "rot0_qm_axuser_nonsecured_regs.h"
80 #include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
81 #include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
82 #include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
83 #include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
84 #include "dcore0_rtr0_ctrl_regs.h"
85 #include "dcore0_dec0_cmd_regs.h"
86 #include "dcore0_vdec0_brdg_ctrl_regs.h"
87 #include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
88 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
89 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
90 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
91 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
92 #include "dcore0_vdec0_ctrl_special_regs.h"
93 #include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
94 #include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
95 #include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
96 #include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
97 #include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
98 #include "pcie_dec0_cmd_regs.h"
99 #include "pcie_vdec0_brdg_ctrl_regs.h"
100 #include "pcie_vdec0_ctrl_special_regs.h"
101 #include "dcore0_mme_qm_regs.h"
102 #include "dcore0_mme_qm_arc_aux_regs.h"
103 #include "dcore0_mme_qm_axuser_secured_regs.h"
104 #include "dcore0_mme_qm_cgm_regs.h"
105 #include "dcore0_mme_qm_arc_acp_eng_regs.h"
106 #include "dcore0_mme_qm_axuser_nonsecured_regs.h"
107 #include "dcore0_mme_qm_arc_dup_eng_regs.h"
108 #include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h"
109 #include "dcore0_mme_sbte0_mstr_if_axuser_regs.h"
110 #include "dcore0_mme_wb0_mstr_if_axuser_regs.h"
111 #include "dcore0_mme_acc_regs.h"
112 #include "dcore0_mme_ctrl_lo_regs.h"
113 #include "dcore1_mme_ctrl_lo_regs.h"
114 #include "dcore3_mme_ctrl_lo_regs.h"
115 #include "dcore0_mme_ctrl_lo_mme_axuser_regs.h"
116 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h"
117 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h"
118 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h"
119 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h"
120 #include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h"
121 #include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h"
122 #include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h"
123 #include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h"
124 #include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h"
125 #include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h"
126 #include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h"
127 #include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h"
128 #include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h"
129 #include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h"
130 #include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h"
131 #include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h"
132 #include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h"
133 #include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h"
134 #include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h"
135 #include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h"
136 #include "pcie_wrap_special_regs.h"
137 
138 #include "pdma0_qm_masks.h"
139 #include "pdma0_core_masks.h"
140 #include "pdma0_core_special_masks.h"
141 #include "psoc_global_conf_masks.h"
142 #include "psoc_reset_conf_masks.h"
143 #include "arc_farm_kdma_masks.h"
144 #include "arc_farm_kdma_ctx_masks.h"
145 #include "arc_farm_arc0_aux_masks.h"
146 #include "arc_farm_kdma_ctx_axuser_masks.h"
147 #include "dcore0_sync_mngr_objs_masks.h"
148 #include "dcore0_sync_mngr_glbl_masks.h"
149 #include "dcore0_sync_mngr_mstr_if_axuser_masks.h"
150 #include "dcore0_tpc0_cfg_masks.h"
151 #include "dcore0_mme_ctrl_lo_masks.h"
152 #include "dcore0_mme_sbte0_masks.h"
153 #include "dcore0_edma0_qm_masks.h"
154 #include "dcore0_edma0_core_masks.h"
155 #include "dcore0_hmmu0_stlb_masks.h"
156 #include "dcore0_hmmu0_mmu_masks.h"
157 #include "dcore0_dec0_cmd_masks.h"
158 #include "dcore0_vdec0_brdg_ctrl_masks.h"
159 #include "pcie_dec0_cmd_masks.h"
160 #include "pcie_vdec0_brdg_ctrl_masks.h"
161 #include "rot0_masks.h"
162 #include "pmmu_hbw_stlb_masks.h"
163 #include "psoc_etr_masks.h"
164 
165 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR	0x4800040
166 
167 #define SM_OBJS_PROT_BITS_OFFS			0x14000
168 
169 #define DCORE_OFFSET			(mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE)
170 #define DCORE_EDMA_OFFSET		(mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE)
171 #define DCORE_TPC_OFFSET		(mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE)
172 #define DCORE_DEC_OFFSET		(mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE)
173 #define DCORE_HMMU_OFFSET		(mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE)
174 #define NIC_QM_OFFSET			(mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
175 #define PDMA_OFFSET			(mmPDMA1_QM_BASE - mmPDMA0_QM_BASE)
176 #define ROT_OFFSET			(mmROT1_BASE - mmROT0_BASE)
177 
178 #define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \
179 			(mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
180 
181 #define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \
182 			(mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
183 
184 #define TPC_CFG_STALL_OFFSET		(mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE)
185 #define TPC_CFG_STALL_ON_ERR_OFFSET	(mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE)
186 #define TPC_CFG_TPC_INTR_MASK_OFFSET	(mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE)
187 #define TPC_CFG_MSS_CONFIG_OFFSET	(mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE)
188 
189 #define MME_ACC_INTR_MASK_OFFSET	(mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE)
190 #define MME_ACC_WR_AXI_AGG_COUT0_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE)
191 #define MME_ACC_WR_AXI_AGG_COUT1_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE)
192 #define MME_ACC_AP_LFSR_POLY_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE)
193 #define MME_ACC_AP_LFSR_SEED_SEL_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE)
194 #define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \
195 	(mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE)
196 
197 #define DMA_CORE_CFG_0_OFFSET		(mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE)
198 #define DMA_CORE_CFG_1_OFFSET		(mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE)
199 #define DMA_CORE_PROT_OFFSET		(mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE)
200 #define DMA_CORE_ERRMSG_ADDR_LO_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE)
201 #define DMA_CORE_ERRMSG_ADDR_HI_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE)
202 #define DMA_CORE_ERRMSG_WDATA_OFFSET	(mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE)
203 
204 #define QM_PQ_BASE_LO_0_OFFSET		(mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE)
205 #define QM_PQ_BASE_HI_0_OFFSET		(mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE)
206 #define QM_PQ_SIZE_0_OFFSET		(mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE)
207 #define QM_PQ_PI_0_OFFSET		(mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE)
208 #define QM_PQ_CI_0_OFFSET		(mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE)
209 #define QM_CP_FENCE0_CNT_0_OFFSET	(mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE)
210 
211 #define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE)
212 #define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE)
213 #define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE)
214 #define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE)
215 
216 #define QM_CP_CFG_OFFSET		(mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE)
217 #define QM_PQC_HBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE)
218 #define QM_PQC_HBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE)
219 #define QM_PQC_SIZE_0_OFFSET		(mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE)
220 #define QM_PQC_PI_0_OFFSET		(mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE)
221 #define QM_PQC_LBW_WDATA_0_OFFSET	(mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE)
222 #define QM_PQC_LBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE)
223 #define QM_PQC_LBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE)
224 #define QM_GLBL_ERR_ADDR_LO_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE)
225 #define QM_PQC_CFG_OFFSET		(mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE)
226 #define QM_ARB_CFG_0_OFFSET		(mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE)
227 #define QM_GLBL_CFG0_OFFSET		(mmPDMA0_QM_GLBL_CFG0 -	mmPDMA0_QM_BASE)
228 #define QM_GLBL_CFG1_OFFSET		(mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE)
229 #define QM_GLBL_CFG2_OFFSET		(mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE)
230 #define QM_GLBL_PROT_OFFSET		(mmPDMA0_QM_GLBL_PROT -	mmPDMA0_QM_BASE)
231 #define QM_GLBL_ERR_CFG_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE)
232 #define QM_GLBL_ERR_CFG1_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE)
233 #define QM_GLBL_ERR_ADDR_HI_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE)
234 #define QM_GLBL_ERR_WDATA_OFFSET	(mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE)
235 #define QM_ARB_ERR_MSG_EN_OFFSET	(mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE)
236 #define QM_ARB_SLV_CHOISE_WDT_OFFSET	(mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE)
237 #define QM_FENCE2_OFFSET		(mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE)
238 #define QM_SEI_STATUS_OFFSET		(mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE)
239 
240 #define SFT_OFFSET		(mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
241 #define SFT_IF_RTR_OFFSET	(mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
242 
243 #define ARC_HALT_REQ_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE)
244 #define ARC_HALT_ACK_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE)
245 
246 #define ARC_REGION_CFG_OFFSET(region) \
247 	(mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE)
248 
249 #define ARC_DCCM_UPPER_EN_OFFSET \
250 	(mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE)
251 
252 #define PCIE_VDEC_OFFSET	\
253 	(mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
254 
255 #define DCORE_MME_SBTE_OFFSET	\
256 	(mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE)
257 
258 #define DCORE_MME_WB_OFFSET	\
259 	(mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE)
260 
261 #define DCORE_RTR_OFFSET	\
262 	(mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
263 
264 #define DCORE_VDEC_OFFSET	\
265 	(mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
266 
267 #define MMU_OFFSET(REG)			(REG - mmDCORE0_HMMU0_MMU_BASE)
268 #define MMU_BYPASS_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS)
269 #define MMU_SPI_SEI_MASK_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK)
270 #define MMU_SPI_SEI_CAUSE_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE)
271 #define MMU_ENABLE_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE)
272 #define MMU_DDR_RANGE_REG_ENABLE	MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE)
273 #define MMU_RR_SEC_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0)
274 #define MMU_RR_SEC_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0)
275 #define MMU_RR_SEC_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0)
276 #define MMU_RR_SEC_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0)
277 #define MMU_RR_PRIV_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0)
278 #define MMU_RR_PRIV_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0)
279 #define MMU_RR_PRIV_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0)
280 #define MMU_RR_PRIV_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0)
281 #define MMU_INTERRUPT_CLR_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR)
282 
283 #define STLB_OFFSET(REG)		(REG - mmDCORE0_HMMU0_STLB_BASE)
284 #define STLB_BUSY_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY)
285 #define STLB_ASID_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID)
286 #define STLB_HOP0_PA43_12_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12)
287 #define STLB_HOP0_PA63_44_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44)
288 #define STLB_HOP_CONFIGURATION_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION)
289 #define STLB_INV_ALL_START_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START)
290 #define STLB_SRAM_INIT_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT)
291 #define STLB_SET_THRESHOLD_HOP3_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3)
292 #define STLB_SET_THRESHOLD_HOP2_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2)
293 #define STLB_SET_THRESHOLD_HOP1_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1)
294 #define STLB_SET_THRESHOLD_HOP0_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0)
295 #define STLB_RANGE_INV_START_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB)
296 #define STLB_RANGE_INV_START_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB)
297 #define STLB_RANGE_INV_END_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB)
298 #define STLB_RANGE_INV_END_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB)
299 
300 #define STLB_LL_LOOKUP_MASK_63_32_OFFSET	\
301 			STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32)
302 
303 #define STLB_RANGE_CACHE_INVALIDATION_OFFSET	\
304 			STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION)
305 
306 /* RTR CTR RAZWI related offsets */
307 #define RTR_MSTR_IF_OFFSET	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
308 
309 #define RTR_LBW_MSTR_IF_OFFSET	\
310 			(mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
311 
312 /* RAZWI captured hbw aw addr high */
313 #define DEC_RAZWI_HBW_AW_ADDR_HI	\
314 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
315 
316 /* RAZWI captured hbw aw addr low */
317 #define DEC_RAZWI_HBW_AW_ADDR_LO	\
318 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
319 
320 /* RAZWI captured hbw aw set */
321 #define DEC_RAZWI_HBW_AW_SET		\
322 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
323 
324 /* RAZWI captured hbw ar addr high */
325 #define DEC_RAZWI_HBW_AR_ADDR_HI \
326 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
327 
328 /* RAZWI captured hbw ar addr low */
329 #define DEC_RAZWI_HBW_AR_ADDR_LO	\
330 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
331 
332 /* RAZWI captured hbw ar set */
333 #define DEC_RAZWI_HBW_AR_SET		\
334 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
335 
336 /* RAZWI captured lbw aw addr */
337 #define DEC_RAZWI_LBW_AW_ADDR		\
338 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE)
339 
340 /* RAZWI captured lbw aw set */
341 #define DEC_RAZWI_LBW_AW_SET		\
342 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
343 
344 /* RAZWI captured lbw ar addr */
345 #define DEC_RAZWI_LBW_AR_ADDR		\
346 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE)
347 
348 /* RAZWI captured lbw ar set */
349 #define DEC_RAZWI_LBW_AR_SET		\
350 			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
351 
352 /* RAZWI captured shared hbw aw addr high */
353 #define RR_SHRD_HBW_AW_RAZWI_HI		\
354 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
355 
356 /* RAZWI captured shared hbw aw addr low */
357 #define RR_SHRD_HBW_AW_RAZWI_LO		\
358 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
359 
360 /* RAZWI captured shared hbw ar addr high */
361 #define RR_SHRD_HBW_AR_RAZWI_HI		\
362 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
363 
364 /* RAZWI captured shared hbw ar addr low */
365 #define RR_SHRD_HBW_AR_RAZWI_LO		\
366 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
367 
368 /* RAZWI captured shared aw XY coordinates */
369 #define RR_SHRD_HBW_AW_RAZWI_XY		\
370 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
371 
372 /* RAZWI captured shared ar XY coordinates */
373 #define RR_SHRD_HBW_AR_RAZWI_XY		\
374 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
375 
376 /* RAZWI hbw shared occurred due to write access */
377 #define RR_SHRD_HBW_AW_RAZWI_HAPPENED	\
378 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \
379 				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
380 
381 /* RAZWI hbw shared occurred due to read access */
382 #define RR_SHRD_HBW_AR_RAZWI_HAPPENED	\
383 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \
384 				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
385 
386 /* RAZWI captured shared lbw aw addr */
387 #define RR_SHRD_LBW_AW_RAZWI		\
388 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \
389 					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
390 
391 /* RAZWI captured shared lbw ar addr */
392 #define RR_SHRD_LBW_AR_RAZWI		\
393 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \
394 					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
395 
396 /* RAZWI captured shared lbw aw XY coordinates */
397 #define RR_SHRD_LBW_AW_RAZWI_XY		\
398 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \
399 					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
400 
401 /* RAZWI captured shared lbw ar XY coordinates */
402 #define RR_SHRD_LBW_AR_RAZWI_XY		\
403 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \
404 					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
405 
406 /* RAZWI lbw shared occurred due to write access */
407 #define RR_SHRD_LBW_AW_RAZWI_HAPPENED	\
408 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \
409 					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
410 
411 /* RAZWI lbw shared occurred due to read access */
412 #define RR_SHRD_LBW_AR_RAZWI_HAPPENED	\
413 			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \
414 				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
415 
416 #define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE)
417 #define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE)
418 #define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
419 #define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
420 
421 #define BRDG_CTRL_NRM_MSIX_LBW_AWADDR	\
422 	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
423 
424 #define BRDG_CTRL_NRM_MSIX_LBW_WDATA	\
425 	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
426 
427 #define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR	\
428 	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
429 
430 #define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA	\
431 	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
432 
433 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET	\
434 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \
435 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
436 
437 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET	\
438 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \
439 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
440 
441 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET	\
442 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \
443 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
444 
445 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET	\
446 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \
447 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
448 
449 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET	\
450 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \
451 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
452 
453 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET	\
454 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \
455 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
456 
457 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET	\
458 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \
459 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
460 
461 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET	\
462 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \
463 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
464 
465 #define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET	\
466 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \
467 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
468 
469 #define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET	\
470 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \
471 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
472 
473 #define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET	\
474 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \
475 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
476 
477 #define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET	\
478 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \
479 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
480 
481 #define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET	\
482 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \
483 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
484 
485 #define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET	\
486 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \
487 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
488 
489 #define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET	\
490 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \
491 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
492 
493 #define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET	\
494 	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \
495 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
496 
497 #define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET	\
498 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \
499 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
500 
501 #define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET	\
502 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \
503 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
504 
505 #define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET	\
506 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \
507 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
508 
509 #define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET	\
510 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \
511 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
512 
513 #define RR_LBW_SEC_RANGE_MIN_0_OFFSET	\
514 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \
515 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
516 
517 #define RR_LBW_SEC_RANGE_MAX_0_OFFSET	\
518 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \
519 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
520 
521 #define RR_LBW_PRIV_RANGE_MIN_0_OFFSET	\
522 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \
523 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
524 
525 #define RR_LBW_PRIV_RANGE_MAX_0_OFFSET	\
526 		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \
527 			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
528 
529 #define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET	\
530 		(mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE)
531 
532 #define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET	\
533 	(mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE)
534 
535 #define HBM_MC_SPI_TEMP_PIN_CHG_MASK		BIT(0)
536 #define HBM_MC_SPI_THR_ENG_MASK			BIT(1)
537 #define HBM_MC_SPI_THR_DIS_ENG_MASK		BIT(2)
538 #define HBM_MC_SPI_IEEE1500_COMP_MASK		BIT(3)
539 #define HBM_MC_SPI_IEEE1500_PAUSED_MASK		BIT(4)
540 
541 #include "nic0_qpc0_regs.h"
542 #include "nic0_qm0_regs.h"
543 #include "nic0_qm_arc_aux0_regs.h"
544 #include "nic0_qm0_cgm_regs.h"
545 #include "nic0_umr0_0_completion_queue_ci_1_regs.h"
546 #include "nic0_umr0_0_unsecure_doorbell0_regs.h"
547 
548 #define NIC_OFFSET		(mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE)
549 
550 #define NIC_UMR_OFFSET \
551 	(mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE)
552 
553 #endif /* ASIC_REG_GAUDI2_REGS_H_ */
554