1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_ 14 #define ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE1_SYNC_MNGR_GLBL 19 * (Prototype: SOB_GLBL) 20 ***************************************** 21 */ 22 23 #define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_MASK 0x431E000 24 25 #define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x431E004 26 27 #define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_L 0x431E008 28 29 #define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_H 0x431E00C 30 31 #define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_L 0x431E020 32 33 #define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_H 0x431E024 34 35 #define mmDCORE1_SYNC_MNGR_GLBL_ASID_SEC 0x431E030 36 37 #define mmDCORE1_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x431E034 38 39 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DELAY 0x431E038 40 41 #define mmDCORE1_SYNC_MNGR_GLBL_PI_SIZE 0x431E03C 42 43 #define mmDCORE1_SYNC_MNGR_GLBL_SOB_ONLY 0x431E040 44 45 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INTR 0x431E044 46 47 #define mmDCORE1_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x431E048 48 49 #define mmDCORE1_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x431E04C 50 51 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x431E050 52 53 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x431E054 54 55 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x431E058 56 57 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x431E05C 58 59 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x431E060 60 61 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x431E064 62 63 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x431E068 64 65 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x431E06C 66 67 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x431E070 68 69 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x431E074 70 71 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x431E078 72 73 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x431E07C 74 75 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x431E080 76 77 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x431E084 78 79 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x431E088 80 81 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x431E08C 82 83 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x431E090 84 85 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x431E094 86 87 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x431E098 88 89 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x431E09C 90 91 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x431E0A0 92 93 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x431E0A4 94 95 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x431E0A8 96 97 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x431E0AC 98 99 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x431E0B0 100 101 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x431E0B4 102 103 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x431E0B8 104 105 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x431E0BC 106 107 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x431E0C0 108 109 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x431E0C4 110 111 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x431E0C8 112 113 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x431E0CC 114 115 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x431E0D0 116 117 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x431E0D4 118 119 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x431E0D8 120 121 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x431E0DC 122 123 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x431E0E0 124 125 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x431E0E4 126 127 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x431E0E8 128 129 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x431E0EC 130 131 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x431E0F0 132 133 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x431E0F4 134 135 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x431E0F8 136 137 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x431E0FC 138 139 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x431E100 140 141 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x431E104 142 143 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x431E108 144 145 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x431E10C 146 147 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x431E110 148 149 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x431E114 150 151 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x431E118 152 153 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x431E11C 154 155 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x431E120 156 157 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x431E124 158 159 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x431E128 160 161 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x431E12C 162 163 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x431E130 164 165 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x431E134 166 167 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x431E138 168 169 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x431E13C 170 171 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x431E140 172 173 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x431E144 174 175 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x431E148 176 177 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x431E14C 178 179 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x431E150 180 181 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x431E154 182 183 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x431E158 184 185 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x431E15C 186 187 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x431E160 188 189 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x431E164 190 191 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x431E168 192 193 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x431E16C 194 195 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x431E170 196 197 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x431E174 198 199 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x431E178 200 201 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x431E17C 202 203 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x431E180 204 205 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x431E184 206 207 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x431E188 208 209 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x431E18C 210 211 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x431E190 212 213 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x431E194 214 215 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x431E198 216 217 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x431E19C 218 219 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x431E1A0 220 221 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x431E1A4 222 223 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x431E1A8 224 225 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x431E1AC 226 227 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x431E1B0 228 229 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x431E1B4 230 231 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x431E1B8 232 233 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x431E1BC 234 235 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x431E1C0 236 237 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x431E1C4 238 239 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x431E1C8 240 241 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x431E1CC 242 243 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x431E1D0 244 245 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x431E1D4 246 247 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x431E1D8 248 249 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x431E1DC 250 251 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x431E1E0 252 253 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x431E1E4 254 255 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x431E1E8 256 257 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x431E1EC 258 259 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x431E1F0 260 261 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x431E1F4 262 263 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x431E1F8 264 265 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x431E1FC 266 267 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x431E200 268 269 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x431E204 270 271 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x431E208 272 273 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x431E20C 274 275 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x431E210 276 277 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x431E214 278 279 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x431E218 280 281 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x431E21C 282 283 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x431E220 284 285 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x431E224 286 287 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x431E228 288 289 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x431E22C 290 291 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x431E230 292 293 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x431E234 294 295 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x431E238 296 297 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x431E23C 298 299 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x431E240 300 301 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x431E244 302 303 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x431E248 304 305 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x431E24C 306 307 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x431E250 308 309 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x431E254 310 311 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x431E258 312 313 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x431E25C 314 315 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x431E260 316 317 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x431E264 318 319 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x431E268 320 321 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x431E26C 322 323 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x431E270 324 325 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x431E274 326 327 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x431E278 328 329 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x431E27C 330 331 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x431E280 332 333 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x431E284 334 335 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x431E288 336 337 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x431E28C 338 339 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x431E290 340 341 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x431E294 342 343 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x431E298 344 345 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x431E29C 346 347 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x431E2A0 348 349 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x431E2A4 350 351 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x431E2A8 352 353 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x431E2AC 354 355 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x431E2B0 356 357 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x431E2B4 358 359 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x431E2B8 360 361 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x431E2BC 362 363 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x431E2C0 364 365 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x431E2C4 366 367 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x431E2C8 368 369 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x431E2CC 370 371 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x431E2D0 372 373 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x431E2D4 374 375 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x431E2D8 376 377 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x431E2DC 378 379 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x431E2E0 380 381 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x431E2E4 382 383 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x431E2E8 384 385 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x431E2EC 386 387 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x431E2F0 388 389 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x431E2F4 390 391 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x431E2F8 392 393 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x431E2FC 394 395 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x431E300 396 397 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x431E304 398 399 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x431E308 400 401 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x431E30C 402 403 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x431E310 404 405 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x431E314 406 407 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x431E318 408 409 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x431E31C 410 411 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x431E320 412 413 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x431E324 414 415 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x431E328 416 417 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x431E32C 418 419 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x431E330 420 421 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x431E334 422 423 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x431E338 424 425 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x431E33C 426 427 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x431E340 428 429 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x431E344 430 431 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x431E348 432 433 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x431E34C 434 435 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0 0x431E350 436 437 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_1 0x431E354 438 439 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_2 0x431E358 440 441 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_3 0x431E35C 442 443 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_4 0x431E360 444 445 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_5 0x431E364 446 447 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_6 0x431E368 448 449 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_7 0x431E36C 450 451 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_8 0x431E370 452 453 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_9 0x431E374 454 455 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_10 0x431E378 456 457 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_11 0x431E37C 458 459 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_12 0x431E380 460 461 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_13 0x431E384 462 463 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_14 0x431E388 464 465 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_15 0x431E38C 466 467 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_16 0x431E390 468 469 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_17 0x431E394 470 471 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_18 0x431E398 472 473 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_19 0x431E39C 474 475 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_20 0x431E3A0 476 477 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_21 0x431E3A4 478 479 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_22 0x431E3A8 480 481 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_23 0x431E3AC 482 483 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_24 0x431E3B0 484 485 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_25 0x431E3B4 486 487 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_26 0x431E3B8 488 489 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_27 0x431E3BC 490 491 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_28 0x431E3C0 492 493 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_29 0x431E3C4 494 495 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_30 0x431E3C8 496 497 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_31 0x431E3CC 498 499 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_32 0x431E3D0 500 501 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_33 0x431E3D4 502 503 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_34 0x431E3D8 504 505 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_35 0x431E3DC 506 507 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_36 0x431E3E0 508 509 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_37 0x431E3E4 510 511 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_38 0x431E3E8 512 513 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_39 0x431E3EC 514 515 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_40 0x431E3F0 516 517 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_41 0x431E3F4 518 519 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_42 0x431E3F8 520 521 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_43 0x431E3FC 522 523 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_44 0x431E400 524 525 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_45 0x431E404 526 527 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_46 0x431E408 528 529 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_47 0x431E40C 530 531 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_48 0x431E410 532 533 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_49 0x431E414 534 535 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_50 0x431E418 536 537 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_51 0x431E41C 538 539 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_52 0x431E420 540 541 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_53 0x431E424 542 543 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_54 0x431E428 544 545 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_55 0x431E42C 546 547 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_56 0x431E430 548 549 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_57 0x431E434 550 551 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_58 0x431E438 552 553 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_59 0x431E43C 554 555 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_60 0x431E440 556 557 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_61 0x431E444 558 559 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_62 0x431E448 560 561 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63 0x431E44C 562 563 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_0 0x431E450 564 565 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_1 0x431E454 566 567 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_2 0x431E458 568 569 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_3 0x431E45C 570 571 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_4 0x431E460 572 573 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_5 0x431E464 574 575 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_6 0x431E468 576 577 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_7 0x431E46C 578 579 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_8 0x431E470 580 581 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_9 0x431E474 582 583 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_10 0x431E478 584 585 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_11 0x431E47C 586 587 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_12 0x431E480 588 589 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_13 0x431E484 590 591 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_14 0x431E488 592 593 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_15 0x431E48C 594 595 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_16 0x431E490 596 597 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_17 0x431E494 598 599 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_18 0x431E498 600 601 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_19 0x431E49C 602 603 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_20 0x431E4A0 604 605 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_21 0x431E4A4 606 607 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_22 0x431E4A8 608 609 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_23 0x431E4AC 610 611 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_24 0x431E4B0 612 613 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_25 0x431E4B4 614 615 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_26 0x431E4B8 616 617 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_27 0x431E4BC 618 619 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_28 0x431E4C0 620 621 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_29 0x431E4C4 622 623 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_30 0x431E4C8 624 625 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_31 0x431E4CC 626 627 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_32 0x431E4D0 628 629 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_33 0x431E4D4 630 631 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_34 0x431E4D8 632 633 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_35 0x431E4DC 634 635 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_36 0x431E4E0 636 637 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_37 0x431E4E4 638 639 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_38 0x431E4E8 640 641 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_39 0x431E4EC 642 643 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_40 0x431E4F0 644 645 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_41 0x431E4F4 646 647 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_42 0x431E4F8 648 649 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_43 0x431E4FC 650 651 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_44 0x431E500 652 653 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_45 0x431E504 654 655 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_46 0x431E508 656 657 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_47 0x431E50C 658 659 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_48 0x431E510 660 661 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_49 0x431E514 662 663 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_50 0x431E518 664 665 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_51 0x431E51C 666 667 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_52 0x431E520 668 669 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_53 0x431E524 670 671 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_54 0x431E528 672 673 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_55 0x431E52C 674 675 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_56 0x431E530 676 677 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_57 0x431E534 678 679 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_58 0x431E538 680 681 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_59 0x431E53C 682 683 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_60 0x431E540 684 685 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_61 0x431E544 686 687 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_62 0x431E548 688 689 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_63 0x431E54C 690 691 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x431E550 692 693 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x431E554 694 695 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x431E558 696 697 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x431E55C 698 699 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x431E560 700 701 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x431E564 702 703 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x431E568 704 705 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x431E56C 706 707 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x431E570 708 709 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x431E574 710 711 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x431E578 712 713 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x431E57C 714 715 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x431E580 716 717 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x431E584 718 719 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x431E588 720 721 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x431E58C 722 723 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x431E590 724 725 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x431E594 726 727 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x431E598 728 729 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x431E59C 730 731 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x431E5A0 732 733 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x431E5A4 734 735 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x431E5A8 736 737 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x431E5AC 738 739 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x431E5B0 740 741 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x431E5B4 742 743 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x431E5B8 744 745 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x431E5BC 746 747 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x431E5C0 748 749 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x431E5C4 750 751 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x431E5C8 752 753 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x431E5CC 754 755 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x431E5D0 756 757 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x431E5D4 758 759 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x431E5D8 760 761 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x431E5DC 762 763 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x431E5E0 764 765 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x431E5E4 766 767 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x431E5E8 768 769 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x431E5EC 770 771 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x431E5F0 772 773 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x431E5F4 774 775 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x431E5F8 776 777 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x431E5FC 778 779 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x431E600 780 781 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x431E604 782 783 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x431E608 784 785 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x431E60C 786 787 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x431E610 788 789 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x431E614 790 791 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x431E618 792 793 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x431E61C 794 795 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x431E620 796 797 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x431E624 798 799 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x431E628 800 801 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x431E62C 802 803 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x431E630 804 805 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x431E634 806 807 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x431E638 808 809 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x431E63C 810 811 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x431E640 812 813 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x431E644 814 815 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x431E648 816 817 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x431E64C 818 819 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x431E650 820 821 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x431E654 822 823 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x431E658 824 825 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x431E65C 826 827 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x431E660 828 829 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x431E664 830 831 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x431E668 832 833 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x431E66C 834 835 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x431E670 836 837 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x431E674 838 839 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x431E678 840 841 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x431E67C 842 843 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x431E680 844 845 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x431E684 846 847 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x431E688 848 849 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x431E68C 850 851 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x431E690 852 853 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x431E694 854 855 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x431E698 856 857 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x431E69C 858 859 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x431E6A0 860 861 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x431E6A4 862 863 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x431E6A8 864 865 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x431E6AC 866 867 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x431E6B0 868 869 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x431E6B4 870 871 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x431E6B8 872 873 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x431E6BC 874 875 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x431E6C0 876 877 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x431E6C4 878 879 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x431E6C8 880 881 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x431E6CC 882 883 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x431E6D0 884 885 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x431E6D4 886 887 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x431E6D8 888 889 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x431E6DC 890 891 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x431E6E0 892 893 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x431E6E4 894 895 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x431E6E8 896 897 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x431E6EC 898 899 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x431E6F0 900 901 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x431E6F4 902 903 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x431E6F8 904 905 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x431E6FC 906 907 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x431E700 908 909 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x431E704 910 911 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x431E708 912 913 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x431E70C 914 915 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x431E710 916 917 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x431E714 918 919 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x431E718 920 921 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x431E71C 922 923 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x431E720 924 925 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x431E724 926 927 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x431E728 928 929 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x431E72C 930 931 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x431E730 932 933 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x431E734 934 935 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x431E738 936 937 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x431E73C 938 939 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x431E740 940 941 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x431E744 942 943 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x431E748 944 945 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x431E74C 946 947 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0 0x431E750 948 949 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_1 0x431E754 950 951 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_2 0x431E758 952 953 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_3 0x431E75C 954 955 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_4 0x431E760 956 957 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_5 0x431E764 958 959 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_6 0x431E768 960 961 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_7 0x431E76C 962 963 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_8 0x431E770 964 965 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_9 0x431E774 966 967 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_10 0x431E778 968 969 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_11 0x431E77C 970 971 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_12 0x431E780 972 973 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_13 0x431E784 974 975 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_14 0x431E788 976 977 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_15 0x431E78C 978 979 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_16 0x431E790 980 981 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_17 0x431E794 982 983 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_18 0x431E798 984 985 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_19 0x431E79C 986 987 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_20 0x431E7A0 988 989 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_21 0x431E7A4 990 991 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_22 0x431E7A8 992 993 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_23 0x431E7AC 994 995 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_24 0x431E7B0 996 997 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_25 0x431E7B4 998 999 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_26 0x431E7B8 1000 1001 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_27 0x431E7BC 1002 1003 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_28 0x431E7C0 1004 1005 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_29 0x431E7C4 1006 1007 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_30 0x431E7C8 1008 1009 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_31 0x431E7CC 1010 1011 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_32 0x431E7D0 1012 1013 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_33 0x431E7D4 1014 1015 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_34 0x431E7D8 1016 1017 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_35 0x431E7DC 1018 1019 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_36 0x431E7E0 1020 1021 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_37 0x431E7E4 1022 1023 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_38 0x431E7E8 1024 1025 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_39 0x431E7EC 1026 1027 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_40 0x431E7F0 1028 1029 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_41 0x431E7F4 1030 1031 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_42 0x431E7F8 1032 1033 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_43 0x431E7FC 1034 1035 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_44 0x431E800 1036 1037 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_45 0x431E804 1038 1039 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_46 0x431E808 1040 1041 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_47 0x431E80C 1042 1043 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_48 0x431E810 1044 1045 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_49 0x431E814 1046 1047 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_50 0x431E818 1048 1049 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_51 0x431E81C 1050 1051 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_52 0x431E820 1052 1053 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_53 0x431E824 1054 1055 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_54 0x431E828 1056 1057 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_55 0x431E82C 1058 1059 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_56 0x431E830 1060 1061 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_57 0x431E834 1062 1063 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_58 0x431E838 1064 1065 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_59 0x431E83C 1066 1067 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_60 0x431E840 1068 1069 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_61 0x431E844 1070 1071 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_62 0x431E848 1072 1073 #define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63 0x431E84C 1074 1075 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x431E850 1076 1077 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x431E854 1078 1079 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x431E858 1080 1081 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x431E85C 1082 1083 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x431E860 1084 1085 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x431E864 1086 1087 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x431E868 1088 1089 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x431E86C 1090 1091 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x431E870 1092 1093 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x431E874 1094 1095 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x431E878 1096 1097 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x431E87C 1098 1099 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x431E880 1100 1101 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x431E884 1102 1103 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x431E888 1104 1105 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x431E88C 1106 1107 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x431E890 1108 1109 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x431E894 1110 1111 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x431E898 1112 1113 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x431E89C 1114 1115 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x431E8A0 1116 1117 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x431E8A4 1118 1119 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x431E8A8 1120 1121 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x431E8AC 1122 1123 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x431E8B0 1124 1125 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x431E8B4 1126 1127 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x431E8B8 1128 1129 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x431E8BC 1130 1131 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x431E8C0 1132 1133 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x431E8C4 1134 1135 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x431E8C8 1136 1137 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x431E8CC 1138 1139 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x431E8D0 1140 1141 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x431E8D4 1142 1143 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x431E8D8 1144 1145 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x431E8DC 1146 1147 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x431E8E0 1148 1149 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x431E8E4 1150 1151 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x431E8E8 1152 1153 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x431E8EC 1154 1155 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x431E8F0 1156 1157 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x431E8F4 1158 1159 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x431E8F8 1160 1161 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x431E8FC 1162 1163 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x431E900 1164 1165 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x431E904 1166 1167 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x431E908 1168 1169 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x431E90C 1170 1171 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x431E910 1172 1173 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x431E914 1174 1175 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x431E918 1176 1177 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x431E91C 1178 1179 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x431E920 1180 1181 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x431E924 1182 1183 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x431E928 1184 1185 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x431E92C 1186 1187 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x431E930 1188 1189 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x431E934 1190 1191 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x431E938 1192 1193 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x431E93C 1194 1195 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x431E940 1196 1197 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x431E944 1198 1199 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x431E948 1200 1201 #define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x431E94C 1202 1203 #endif /* ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_ */ 1204