1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_TPC0_QM_ARC_AUX 19*e65e175bSOded Gabbay * (Prototype: QMAN_ARC_AUX) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218 160*e65e175bSOded Gabbay 161*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220 164*e65e175bSOded Gabbay 165*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C 170*e65e175bSOded Gabbay 171*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234 174*e65e175bSOded Gabbay 175*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C 178*e65e175bSOded Gabbay 179*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298 188*e65e175bSOded Gabbay 189*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0 192*e65e175bSOded Gabbay 193*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4 194*e65e175bSOded Gabbay 195*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8 196*e65e175bSOded Gabbay 197*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4 200*e65e175bSOded Gabbay 201*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8 202*e65e175bSOded Gabbay 203*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC 204*e65e175bSOded Gabbay 205*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0 206*e65e175bSOded Gabbay 207*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4 208*e65e175bSOded Gabbay 209*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8 210*e65e175bSOded Gabbay 211*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC 212*e65e175bSOded Gabbay 213*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0 214*e65e175bSOded Gabbay 215*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4 218*e65e175bSOded Gabbay 219*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC 222*e65e175bSOded Gabbay 223*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0 224*e65e175bSOded Gabbay 225*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4 226*e65e175bSOded Gabbay 227*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304 230*e65e175bSOded Gabbay 231*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308 232*e65e175bSOded Gabbay 233*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C 234*e65e175bSOded Gabbay 235*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310 236*e65e175bSOded Gabbay 237*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314 238*e65e175bSOded Gabbay 239*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318 240*e65e175bSOded Gabbay 241*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C 242*e65e175bSOded Gabbay 243*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320 244*e65e175bSOded Gabbay 245*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324 246*e65e175bSOded Gabbay 247*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328 248*e65e175bSOded Gabbay 249*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C 250*e65e175bSOded Gabbay 251*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330 252*e65e175bSOded Gabbay 253*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334 254*e65e175bSOded Gabbay 255*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338 256*e65e175bSOded Gabbay 257*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C 258*e65e175bSOded Gabbay 259*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350 260*e65e175bSOded Gabbay 261*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354 262*e65e175bSOded Gabbay 263*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358 264*e65e175bSOded Gabbay 265*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C 266*e65e175bSOded Gabbay 267*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360 268*e65e175bSOded Gabbay 269*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364 270*e65e175bSOded Gabbay 271*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368 272*e65e175bSOded Gabbay 273*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C 274*e65e175bSOded Gabbay 275*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370 276*e65e175bSOded Gabbay 277*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374 278*e65e175bSOded Gabbay 279*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378 280*e65e175bSOded Gabbay 281*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C 282*e65e175bSOded Gabbay 283*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380 284*e65e175bSOded Gabbay 285*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384 286*e65e175bSOded Gabbay 287*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C 288*e65e175bSOded Gabbay 289*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390 290*e65e175bSOded Gabbay 291*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400 292*e65e175bSOded Gabbay 293*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404 294*e65e175bSOded Gabbay 295*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408 296*e65e175bSOded Gabbay 297*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C 298*e65e175bSOded Gabbay 299*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420 300*e65e175bSOded Gabbay 301*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424 302*e65e175bSOded Gabbay 303*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428 304*e65e175bSOded Gabbay 305*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C 306*e65e175bSOded Gabbay 307*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430 308*e65e175bSOded Gabbay 309*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434 310*e65e175bSOded Gabbay 311*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C 312*e65e175bSOded Gabbay 313*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440 314*e65e175bSOded Gabbay 315*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500 316*e65e175bSOded Gabbay 317*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504 318*e65e175bSOded Gabbay 319*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508 320*e65e175bSOded Gabbay 321*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C 322*e65e175bSOded Gabbay 323*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510 324*e65e175bSOded Gabbay 325*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514 326*e65e175bSOded Gabbay 327*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518 328*e65e175bSOded Gabbay 329*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C 330*e65e175bSOded Gabbay 331*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520 332*e65e175bSOded Gabbay 333*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524 334*e65e175bSOded Gabbay 335*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528 336*e65e175bSOded Gabbay 337*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C 338*e65e175bSOded Gabbay 339*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530 340*e65e175bSOded Gabbay 341*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534 342*e65e175bSOded Gabbay 343*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538 344*e65e175bSOded Gabbay 345*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C 346*e65e175bSOded Gabbay 347*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540 348*e65e175bSOded Gabbay 349*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544 350*e65e175bSOded Gabbay 351*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548 352*e65e175bSOded Gabbay 353*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C 354*e65e175bSOded Gabbay 355*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550 356*e65e175bSOded Gabbay 357*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554 358*e65e175bSOded Gabbay 359*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558 360*e65e175bSOded Gabbay 361*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C 362*e65e175bSOded Gabbay 363*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560 364*e65e175bSOded Gabbay 365*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564 366*e65e175bSOded Gabbay 367*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568 368*e65e175bSOded Gabbay 369*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C 370*e65e175bSOded Gabbay 371*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570 372*e65e175bSOded Gabbay 373*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574 374*e65e175bSOded Gabbay 375*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578 376*e65e175bSOded Gabbay 377*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C 378*e65e175bSOded Gabbay 379*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580 380*e65e175bSOded Gabbay 381*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584 382*e65e175bSOded Gabbay 383*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588 384*e65e175bSOded Gabbay 385*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C 386*e65e175bSOded Gabbay 387*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590 388*e65e175bSOded Gabbay 389*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594 390*e65e175bSOded Gabbay 391*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598 392*e65e175bSOded Gabbay 393*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C 394*e65e175bSOded Gabbay 395*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0 396*e65e175bSOded Gabbay 397*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4 398*e65e175bSOded Gabbay 399*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8 400*e65e175bSOded Gabbay 401*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC 402*e65e175bSOded Gabbay 403*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0 404*e65e175bSOded Gabbay 405*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4 406*e65e175bSOded Gabbay 407*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8 408*e65e175bSOded Gabbay 409*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC 410*e65e175bSOded Gabbay 411*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0 412*e65e175bSOded Gabbay 413*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4 414*e65e175bSOded Gabbay 415*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8 416*e65e175bSOded Gabbay 417*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC 418*e65e175bSOded Gabbay 419*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0 420*e65e175bSOded Gabbay 421*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4 422*e65e175bSOded Gabbay 423*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8 424*e65e175bSOded Gabbay 425*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC 426*e65e175bSOded Gabbay 427*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0 428*e65e175bSOded Gabbay 429*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4 430*e65e175bSOded Gabbay 431*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620 432*e65e175bSOded Gabbay 433*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624 434*e65e175bSOded Gabbay 435*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628 436*e65e175bSOded Gabbay 437*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630 438*e65e175bSOded Gabbay 439*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634 440*e65e175bSOded Gabbay 441*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638 442*e65e175bSOded Gabbay 443*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C 444*e65e175bSOded Gabbay 445*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640 446*e65e175bSOded Gabbay 447*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644 448*e65e175bSOded Gabbay 449*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648 450*e65e175bSOded Gabbay 451*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C 452*e65e175bSOded Gabbay 453*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650 454*e65e175bSOded Gabbay 455*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654 456*e65e175bSOded Gabbay 457*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658 458*e65e175bSOded Gabbay 459*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C 460*e65e175bSOded Gabbay 461*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700 462*e65e175bSOded Gabbay 463*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704 464*e65e175bSOded Gabbay 465*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708 466*e65e175bSOded Gabbay 467*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C 468*e65e175bSOded Gabbay 469*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710 470*e65e175bSOded Gabbay 471*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714 472*e65e175bSOded Gabbay 473*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718 474*e65e175bSOded Gabbay 475*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C 476*e65e175bSOded Gabbay 477*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720 478*e65e175bSOded Gabbay 479*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724 480*e65e175bSOded Gabbay 481*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728 482*e65e175bSOded Gabbay 483*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C 484*e65e175bSOded Gabbay 485*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730 486*e65e175bSOded Gabbay 487*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734 488*e65e175bSOded Gabbay 489*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738 490*e65e175bSOded Gabbay 491*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C 492*e65e175bSOded Gabbay 493*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740 494*e65e175bSOded Gabbay 495*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750 496*e65e175bSOded Gabbay 497*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754 498*e65e175bSOded Gabbay 499*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758 500*e65e175bSOded Gabbay 501*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C 502*e65e175bSOded Gabbay 503*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760 504*e65e175bSOded Gabbay 505*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764 506*e65e175bSOded Gabbay 507*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768 508*e65e175bSOded Gabbay 509*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C 510*e65e175bSOded Gabbay 511*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770 512*e65e175bSOded Gabbay 513*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774 514*e65e175bSOded Gabbay 515*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778 516*e65e175bSOded Gabbay 517*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C 518*e65e175bSOded Gabbay 519*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780 520*e65e175bSOded Gabbay 521*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784 522*e65e175bSOded Gabbay 523*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788 524*e65e175bSOded Gabbay 525*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C 526*e65e175bSOded Gabbay 527*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790 528*e65e175bSOded Gabbay 529*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794 530*e65e175bSOded Gabbay 531*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798 532*e65e175bSOded Gabbay 533*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C 534*e65e175bSOded Gabbay 535*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800 536*e65e175bSOded Gabbay 537*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804 538*e65e175bSOded Gabbay 539*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808 540*e65e175bSOded Gabbay 541*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C 542*e65e175bSOded Gabbay 543*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810 544*e65e175bSOded Gabbay 545*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814 546*e65e175bSOded Gabbay 547*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818 548*e65e175bSOded Gabbay 549*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C 550*e65e175bSOded Gabbay 551*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820 552*e65e175bSOded Gabbay 553*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824 554*e65e175bSOded Gabbay 555*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828 556*e65e175bSOded Gabbay 557*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C 558*e65e175bSOded Gabbay 559*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830 560*e65e175bSOded Gabbay 561*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834 562*e65e175bSOded Gabbay 563*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838 564*e65e175bSOded Gabbay 565*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C 566*e65e175bSOded Gabbay 567*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840 568*e65e175bSOded Gabbay 569*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844 570*e65e175bSOded Gabbay 571*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848 572*e65e175bSOded Gabbay 573*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C 574*e65e175bSOded Gabbay 575*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850 576*e65e175bSOded Gabbay 577*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854 578*e65e175bSOded Gabbay 579*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900 580*e65e175bSOded Gabbay 581*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904 582*e65e175bSOded Gabbay 583*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908 584*e65e175bSOded Gabbay 585*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C 586*e65e175bSOded Gabbay 587*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910 588*e65e175bSOded Gabbay 589*e65e175bSOded Gabbay #define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920 590*e65e175bSOded Gabbay 591*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */ 592