1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_EML_SPMU
19  *   (Prototype: SPMU)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
24 
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
26 
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
28 
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
30 
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
32 
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
34 
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
36 
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
38 
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
40 
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
42 
43 #define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208
44 
45 #define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C
46 
47 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400
48 
49 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404
50 
51 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408
52 
53 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C
54 
55 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410
56 
57 #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414
58 
59 #define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610
60 
61 #define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614
62 
63 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618
64 
65 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C
66 
67 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620
68 
69 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624
70 
71 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628
72 
73 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C
74 
75 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630
76 
77 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634
78 
79 #define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0
80 
81 #define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4
82 
83 #define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00
84 
85 #define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20
86 
87 #define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40
88 
89 #define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60
90 
91 #define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80
92 
93 #define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0
94 
95 #define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0
96 
97 #define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00
98 
99 #define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04
100 
101 #define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00
102 
103 #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0
104 
105 #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4
106 
107 #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8
108 
109 #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC
110 
111 #define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0
112 
113 #define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4
114 
115 #define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8
116 
117 #define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC
118 
119 #define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0
120 
121 #define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4
122 
123 #define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8
124 
125 #define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC
126 
127 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0
128 
129 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4
130 
131 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8
132 
133 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC
134 
135 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0
136 
137 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4
138 
139 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8
140 
141 #define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC
142 
143 #define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0
144 
145 #define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4
146 
147 #define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8
148 
149 #define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC
150 
151 #endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */
152