xref: /openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_busmon_0_regs.h (revision e65e175b)

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_
#define ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_EML_BUSMON_0
 *   (Prototype: BMON)
 *****************************************
 */

#define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000

#define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004

#define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008

#define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E1 0x7038

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E1 0x703C

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S2 0x7040

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S2 0x7044

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E2 0x7048

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E2 0x704C

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S3 0x7050

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S3 0x7054

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E3 0x7058

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E3 0x705C

#define mmDCORE0_TPC0_EML_BUSMON_0_REDUCTION 0x7060

#define mmDCORE0_TPC0_EML_BUSMON_0_IDL 0x7070

#define mmDCORE0_TPC0_EML_BUSMON_0_IDH 0x7074

#define mmDCORE0_TPC0_EML_BUSMON_0_IDENL 0x7078

#define mmDCORE0_TPC0_EML_BUSMON_0_IDENH 0x707C

#define mmDCORE0_TPC0_EML_BUSMON_0_LATENCY_SMP 0x7090

#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR 0x7100

#define mmDCORE0_TPC0_EML_BUSMON_0_ATTREN 0x7104

#define mmDCORE0_TPC0_EML_BUSMON_0_USRENL 0x7108

#define mmDCORE0_TPC0_EML_BUSMON_0_USRL 0x710C

#define mmDCORE0_TPC0_EML_BUSMON_0_USRENH 0x7120

#define mmDCORE0_TPC0_EML_BUSMON_0_USRH 0x7124

#define mmDCORE0_TPC0_EML_BUSMON_0_CAPTURE 0x7200

#define mmDCORE0_TPC0_EML_BUSMON_0_RELEASE 0x7204

#define mmDCORE0_TPC0_EML_BUSMON_0_WIN_CAPTURE 0x7208

#define mmDCORE0_TPC0_EML_BUSMON_0_BW_WIN 0x720C

#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_SOD 0x7220

#define mmDCORE0_TPC0_EML_BUSMON_0_MATCH_CNT_WIN 0x7224

#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_L 0x7228

#define mmDCORE0_TPC0_EML_BUSMON_0_CYCCNT_H 0x722C

#define mmDCORE0_TPC0_EML_BUSMON_0_MAXLAT_SOD 0x7304

#define mmDCORE0_TPC0_EML_BUSMON_0_MINLAT_SOD 0x7308

#define mmDCORE0_TPC0_EML_BUSMON_0_MAXBW_SOD 0x7310

#define mmDCORE0_TPC0_EML_BUSMON_0_MINBW_SOD 0x7314

#define mmDCORE0_TPC0_EML_BUSMON_0_MAXOS_SOD 0x7320

#define mmDCORE0_TPC0_EML_BUSMON_0_MINOS_SOD 0x7324

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_SNAPSHOT 0x7400

#define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_SNAPSHOT 0x7404

#define mmDCORE0_TPC0_EML_BUSMON_0_IDL_SNAPSHOT 0x7408

#define mmDCORE0_TPC0_EML_BUSMON_0_IDH_SNAPSHOT 0x740C

#define mmDCORE0_TPC0_EML_BUSMON_0_ATTR_SNAPSHOT 0x7410

#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC 0x7420

#define mmDCORE0_TPC0_EML_BUSMON_0_STM_TRC_DROP 0x7424

#define mmDCORE0_TPC0_EML_BUSMON_0_DEVARCH 0x7FBC

#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID2 0x7FC0

#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID1 0x7FC4

#define mmDCORE0_TPC0_EML_BUSMON_0_PMDEVID 0x7FC8

#define mmDCORE0_TPC0_EML_BUSMON_0_DEVTYPE 0x7FCC

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR4 0x7FD0

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR5 0x7FD4

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR6 0x7FD8

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR7 0x7FDC

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR0 0x7FE0

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR1 0x7FE4

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR2 0x7FE8

#define mmDCORE0_TPC0_EML_BUSMON_0_PIDR3 0x7FEC

#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR0 0x7FF0

#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR1 0x7FF4

#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR2 0x7FF8

#define mmDCORE0_TPC0_EML_BUSMON_0_CIDR3 0x7FFC

#endif /* ASIC_REG_DCORE0_TPC0_EML_BUSMON_0_REGS_H_ */