1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ 14 #define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_TPC0_CFG_SPECIAL 19 * (Prototype: SPECIAL_REGS) 20 ***************************************** 21 */ 22 23 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80 24 25 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84 26 27 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88 28 29 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C 30 31 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90 32 33 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94 34 35 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98 36 37 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C 38 39 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0 40 41 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4 42 43 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8 44 45 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC 46 47 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0 48 49 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4 50 51 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8 52 53 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC 54 55 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0 56 57 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4 58 59 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8 60 61 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC 62 63 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0 64 65 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4 66 67 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8 68 69 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC 70 71 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0 72 73 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4 74 75 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8 76 77 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC 78 79 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0 80 81 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4 82 83 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8 84 85 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC 86 87 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00 88 89 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04 90 91 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C 92 93 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10 94 95 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14 96 97 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18 98 99 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C 100 101 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20 102 103 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24 104 105 #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28 106 107 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40 108 109 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44 110 111 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48 112 113 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60 114 115 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64 116 117 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68 118 119 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C 120 121 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80 122 123 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84 124 125 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88 126 127 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C 128 129 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90 130 131 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94 132 133 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98 134 135 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C 136 137 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0 138 139 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4 140 141 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8 142 143 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC 144 145 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0 146 147 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4 148 149 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8 150 151 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC 152 153 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0 154 155 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4 156 157 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8 158 159 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC 160 161 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0 162 163 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4 164 165 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8 166 167 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC 168 169 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0 170 171 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4 172 173 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8 174 175 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC 176 177 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0 178 179 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4 180 181 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8 182 183 #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC 184 185 #endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */ 186