1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_TPC0_CFG 19*e65e175bSOded Gabbay * (Prototype: TPC) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT 0x400BCB8 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT 0x400BCBC 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO 0x400BCC0 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI 0x400BCC4 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO 0x400BCC8 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI 0x400BCCC 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO 0x400BCD0 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI 0x400BCD4 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO 0x400BCD8 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI 0x400BCDC 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM 0x400BCE0 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL 0x400BCE4 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 0x400BCE8 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 0x400BCEC 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 0x400BCF0 132*e65e175bSOded Gabbay 133*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 0x400BCF4 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 0x400BCF8 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 0x400BCFC 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 0x400BD00 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 0x400BD04 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 0x400BD08 144*e65e175bSOded Gabbay 145*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 0x400BD0C 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 0x400BD10 148*e65e175bSOded Gabbay 149*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 0x400BD14 150*e65e175bSOded Gabbay 151*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_FP8_143_BIAS 0x400BD64 152*e65e175bSOded Gabbay 153*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ROUND_CSR 0x400BD68 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_HB_PROT 0x400BD6C 156*e65e175bSOded Gabbay 157*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LB_PROT 0x400BD70 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_SEMAPHORE 0x400BD74 160*e65e175bSOded Gabbay 161*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_VFLAGS 0x400BD78 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_SFLAGS 0x400BD7C 164*e65e175bSOded Gabbay 165*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LFSR_POLYNOM 0x400BD80 166*e65e175bSOded Gabbay 167*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_STATUS 0x400BD84 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH 0x400BD88 170*e65e175bSOded Gabbay 171*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE 0x400BD8C 172*e65e175bSOded Gabbay 173*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH 0x400BD90 174*e65e175bSOded Gabbay 175*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_CMD 0x400BD94 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_EXECUTE 0x400BD98 178*e65e175bSOded Gabbay 179*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_STALL 0x400BD9C 180*e65e175bSOded Gabbay 181*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0x400BDA0 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0x400BDA4 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT 0x400BDA8 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT 0x400BDAC 188*e65e175bSOded Gabbay 189*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_MSS_CONFIG 0x400BDB0 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE 0x400BDB4 192*e65e175bSOded Gabbay 193*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TPC_INTR_MASK 0x400BDB8 194*e65e175bSOded Gabbay 195*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_WQ_CREDITS 0x400BDBC 196*e65e175bSOded Gabbay 197*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_OPCODE_EXEC 0x400BDC0 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0x400BDC4 200*e65e175bSOded Gabbay 201*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0x400BDC8 202*e65e175bSOded Gabbay 203*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0x400BDCC 204*e65e175bSOded Gabbay 205*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0x400BDD0 206*e65e175bSOded Gabbay 207*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0x400BDD4 208*e65e175bSOded Gabbay 209*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0x400BDD8 210*e65e175bSOded Gabbay 211*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0x400BDDC 212*e65e175bSOded Gabbay 213*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0x400BDE0 214*e65e175bSOded Gabbay 215*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE 0x400BDE4 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_CFG 0x400BDE8 218*e65e175bSOded Gabbay 219*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR 0x400BDEC 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR 0x400BDF0 222*e65e175bSOded Gabbay 223*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR 0x400BDF4 224*e65e175bSOded Gabbay 225*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR 0x400BDF8 226*e65e175bSOded Gabbay 227*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR 0x400BDFC 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */ 230