1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_TPC0_CFG_QM_TENSOR_0 19*e65e175bSOded Gabbay * (Prototype: TPC_TENSOR) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0x400B5DC 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0x400B5E0 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0x400B5E4 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0x400B5E8 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0x400B5EC 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0x400B5F0 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0x400B5F4 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0x400B5F8 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0x400B5FC 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0x400B600 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0x400B604 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0x400B608 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0x400B60C 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0x400B610 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE 0x400B614 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B618 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B61C 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B620 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B624 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B628 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ */ 64