1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_TPC0_CFG_QM 19*e65e175bSOded Gabbay * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C 108*e65e175bSOded Gabbay 109*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94 112*e65e175bSOded Gabbay 113*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C 116*e65e175bSOded Gabbay 117*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4 120*e65e175bSOded Gabbay 121*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC 124*e65e175bSOded Gabbay 125*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4 128*e65e175bSOded Gabbay 129*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */ 130