1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_CFG_KERNEL
19  *   (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0x400B508
24 
25 #define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x400B50C
26 
27 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_0 0x400B510
28 
29 #define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_0 0x400B514
30 
31 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_1 0x400B518
32 
33 #define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_1 0x400B51C
34 
35 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_2 0x400B520
36 
37 #define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_2 0x400B524
38 
39 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_3 0x400B528
40 
41 #define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_3 0x400B52C
42 
43 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_DIM_4 0x400B530
44 
45 #define mmDCORE0_TPC0_CFG_KERNEL_TID_SIZE_DIM_4 0x400B534
46 
47 #define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG 0x400B538
48 
49 #define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID 0x400B53C
50 
51 #define mmDCORE0_TPC0_CFG_KERNEL_POWER_LOOP 0x400B540
52 
53 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_0 0x400B544
54 
55 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_1 0x400B548
56 
57 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_2 0x400B54C
58 
59 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_3 0x400B550
60 
61 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_4 0x400B554
62 
63 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_5 0x400B558
64 
65 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_6 0x400B55C
66 
67 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_7 0x400B560
68 
69 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_8 0x400B564
70 
71 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_9 0x400B568
72 
73 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_10 0x400B56C
74 
75 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_11 0x400B570
76 
77 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_12 0x400B574
78 
79 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_13 0x400B578
80 
81 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_14 0x400B57C
82 
83 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_15 0x400B580
84 
85 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_16 0x400B584
86 
87 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_17 0x400B588
88 
89 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_18 0x400B58C
90 
91 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_19 0x400B590
92 
93 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_20 0x400B594
94 
95 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_21 0x400B598
96 
97 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_22 0x400B59C
98 
99 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_23 0x400B5A0
100 
101 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_24 0x400B5A4
102 
103 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_25 0x400B5A8
104 
105 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_26 0x400B5AC
106 
107 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_27 0x400B5B0
108 
109 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_28 0x400B5B4
110 
111 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_29 0x400B5B8
112 
113 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_30 0x400B5BC
114 
115 #define mmDCORE0_TPC0_CFG_KERNEL_SRF_31 0x400B5C0
116 
117 #define mmDCORE0_TPC0_CFG_KERNEL_KERNEL_ID_INC 0x400B5C4
118 
119 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x400B5C8
120 
121 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x400B5CC
122 
123 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x400B5D0
124 
125 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x400B5D4
126 
127 #define mmDCORE0_TPC0_CFG_KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x400B5D8
128 
129 #endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_REGS_H_ */
130