1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_MME_SBTE0_MSTR_IF_AXUSER 19*e65e175bSOded Gabbay * (Prototype: AXUSER) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_ASID 0x40D1A80 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_MMU_BP 0x40D1A84 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_STRONG_ORDER 0x40D1A88 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_NO_SNOOP 0x40D1A8C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_REDUCTION 0x40D1A90 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_ATOMIC 0x40D1A94 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_QOS 0x40D1A98 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RSVD 0x40D1A9C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_EMEM_CPAGE 0x40D1AA0 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_CORE 0x40D1AA4 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_E2E_COORD 0x40D1AA8 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_LO 0x40D1AB0 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_WR_OVRD_HI 0x40D1AB4 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_LO 0x40D1AB8 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_HB_RD_OVRD_HI 0x40D1ABC 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_COORD 0x40D1AC0 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_LOCK 0x40D1AC4 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_RSVD 0x40D1AC8 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_LB_OVRD 0x40D1ACC 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_MME_SBTE0_MSTR_IF_AXUSER_REGS_H_ */ 62