1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_MME_SBTE0 19*e65e175bSOded Gabbay * (Prototype: SB) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_MAX_SIZE */ 24*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_SIZE_DATA_SHIFT 0 25*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_SIZE_DATA_MASK 0xFFFF 26*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_SIZE_MD_SHIFT 16 27*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_SIZE_MD_MASK 0xFFFF0000 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_FORCE_MISS */ 30*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_FORCE_MISS_R_SHIFT 0 31*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_FORCE_MISS_R_MASK 0x1 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_MAX */ 34*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_OS_SHIFT 0 35*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_MAX_OS_MASK 0xFFFF 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_RL */ 38*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_SATURATION_SHIFT 0 39*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_SATURATION_MASK 0xFF 40*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_TIMEOUT_SHIFT 8 41*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_TIMEOUT_MASK 0xFF00 42*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_SHIFT 16 43*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_MASK 0x10000 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_SB_STALL */ 46*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_SB_STALL_R_SHIFT 0 47*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_SB_STALL_R_MASK 0x1 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_INTR */ 50*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTR_I0_SHIFT 0 51*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTR_I0_MASK 0x1 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_ARUSER */ 54*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_ASID_SHIFT 0 55*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_ASID_MASK 0x3FF 56*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_MMBP_SHIFT 10 57*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_MMBP_MASK 0x400 58*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_DUMMY_SHIFT 11 59*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_DUMMY_MASK 0xFFFFF800 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_ARCACHE */ 62*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARCACHE_N_SHIFT 0 63*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARCACHE_N_MASK 0xF 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_STATUS */ 66*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_STATUS_DROP_CNT_SHIFT 0 67*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_STATUS_DROP_CNT_MASK 0xFFFFFFFF 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_PRTN */ 70*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_PRTN_CLK_EN_SHIFT 0 71*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_PRTN_CLK_EN_MASK 0x1 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS */ 74*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_SHIFT 0 75*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_MASK 0xFFFFFFFF 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_PROT */ 78*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_PROT_W_SHIFT 0 79*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_PROT_W_MASK 0x7 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_INTR_MASK */ 82*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTR_MASK_W_SHIFT 0 83*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTR_MASK_W_MASK 0x1 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_ARUSER_MSB */ 86*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_SHIFT 0 87*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_MASK 0xFFFFFFFF 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY */ 90*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_SHIFT 0 91*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_MASK 0xFFFFFFFF 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_ENABLE_CGATE */ 94*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_SHIFT 0 95*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_MASK 0x1 96*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_SHIFT 4 97*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_MASK 0x10 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_INTF_VLD_DBG */ 100*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_SHIFT 0 101*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_MASK 0xFFFFFFFF 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay /* DCORE0_MME_SBTE0_INTF_RDY_DBG */ 104*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_SHIFT 0 105*e65e175bSOded Gabbay #define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_MASK 0xFFFFFFFF 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ */ 108