1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ 14 #define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_MME_QM_ARC_DUP_ENG 19 * (Prototype: ARC_DUP_ENG) 20 ***************************************** 21 */ 22 23 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0 0x40C9000 24 25 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_1 0x40C9004 26 27 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_2 0x40C9008 28 29 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_3 0x40C900C 30 31 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_4 0x40C9010 32 33 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_5 0x40C9014 34 35 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_6 0x40C9018 36 37 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_7 0x40C901C 38 39 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_8 0x40C9020 40 41 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_9 0x40C9024 42 43 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_10 0x40C9028 44 45 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_11 0x40C902C 46 47 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_12 0x40C9030 48 49 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_13 0x40C9034 50 51 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_14 0x40C9038 52 53 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_15 0x40C903C 54 55 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_16 0x40C9040 56 57 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_17 0x40C9044 58 59 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_18 0x40C9048 60 61 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_19 0x40C904C 62 63 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_20 0x40C9050 64 65 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_21 0x40C9054 66 67 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_22 0x40C9058 68 69 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_23 0x40C905C 70 71 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_24 0x40C9060 72 73 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_0 0x40C9064 74 75 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_1 0x40C9068 76 77 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_2 0x40C906C 78 79 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_3 0x40C9070 80 81 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_0 0x40C9074 82 83 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_1 0x40C9078 84 85 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_2 0x40C907C 86 87 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_3 0x40C9080 88 89 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_4 0x40C9084 90 91 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_5 0x40C9088 92 93 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_6 0x40C908C 94 95 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_7 0x40C9090 96 97 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_8 0x40C9094 98 99 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_9 0x40C9098 100 101 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_10 0x40C909C 102 103 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_11 0x40C90A0 104 105 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_12 0x40C90A4 106 107 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_13 0x40C90A8 108 109 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_14 0x40C90AC 110 111 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_15 0x40C90B0 112 113 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_16 0x40C90B4 114 115 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_17 0x40C90B8 116 117 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_18 0x40C90BC 118 119 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_19 0x40C90C0 120 121 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_20 0x40C90C4 122 123 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_21 0x40C90C8 124 125 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_22 0x40C90CC 126 127 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_23 0x40C90D0 128 129 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_0 0x40C90D4 130 131 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_1 0x40C90D8 132 133 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_2 0x40C90DC 134 135 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_3 0x40C90E0 136 137 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_4 0x40C90E4 138 139 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_5 0x40C90E8 140 141 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_6 0x40C90EC 142 143 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_7 0x40C90F0 144 145 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_0 0x40C90F4 146 147 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_1 0x40C90F8 148 149 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_0 0x40C90FC 150 151 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_1 0x40C9100 152 153 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_0 0x40C9104 154 155 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_1 0x40C9108 156 157 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_2 0x40C910C 158 159 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_3 0x40C9110 160 161 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_4 0x40C9114 162 163 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_5 0x40C9118 164 165 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_6 0x40C911C 166 167 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_7 0x40C9120 168 169 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_8 0x40C9124 170 171 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_9 0x40C9128 172 173 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_10 0x40C912C 174 175 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_11 0x40C9130 176 177 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_12 0x40C9134 178 179 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_13 0x40C9138 180 181 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_14 0x40C913C 182 183 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_15 0x40C9140 184 185 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_MASK 0x40C9200 186 187 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_MASK 0x40C9204 188 189 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_MASK 0x40C9208 190 191 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_MASK 0x40C920C 192 193 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_MASK 0x40C9210 194 195 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_MASK 0x40C9214 196 197 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_0 0x40C9218 198 199 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_1 0x40C921C 200 201 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_2 0x40C9220 202 203 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_3 0x40C9224 204 205 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_4 0x40C9228 206 207 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_5 0x40C922C 208 209 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_6 0x40C9230 210 211 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_7 0x40C9234 212 213 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_0 0x40C9238 214 215 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_1 0x40C923C 216 217 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_2 0x40C9240 218 219 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_3 0x40C9244 220 221 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_4 0x40C9248 222 223 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_5 0x40C924C 224 225 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_6 0x40C9250 226 227 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_7 0x40C9254 228 229 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_8 0x40C9258 230 231 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_9 0x40C925C 232 233 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_10 0x40C9260 234 235 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_11 0x40C9264 236 237 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_12 0x40C9268 238 239 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_13 0x40C926C 240 241 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_0 0x40C9288 242 243 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_1 0x40C928C 244 245 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_2 0x40C9290 246 247 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_3 0x40C9294 248 249 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_4 0x40C9298 250 251 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_5 0x40C929C 252 253 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_0 0x40C92A0 254 255 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_1 0x40C92A4 256 257 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_2 0x40C92A8 258 259 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_3 0x40C92AC 260 261 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_4 0x40C92B0 262 263 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_5 0x40C92B4 264 265 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_0 0x40C92B8 266 267 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_1 0x40C92BC 268 269 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_2 0x40C92C0 270 271 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_3 0x40C92C4 272 273 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_4 0x40C92C8 274 275 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_5 0x40C92CC 276 277 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GENERAL_CFG 0x40C92D0 278 279 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_BP_CFG 0x40C92D4 280 281 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 0x40C92D8 282 283 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 0x40C92DC 284 285 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 0x40C92E0 286 287 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 0x40C92E4 288 289 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 0x40C92E8 290 291 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 0x40C92EC 292 293 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 0x40C92F0 294 295 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 0x40C92F4 296 297 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 0x40C92F8 298 299 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 0x40C92FC 300 301 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 0x40C9300 302 303 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 0x40C9304 304 305 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 0x40C9308 306 307 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 0x40C930C 308 309 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 0x40C94A0 310 311 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 0x40C94A4 312 313 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 0x40C94A8 314 315 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_STS 0x40C94AC 316 317 #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_OUT_RQ_CNT 0x40C94B0 318 319 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_0 0x40C94B4 320 321 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_1 0x40C94B8 322 323 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_2 0x40C94BC 324 325 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_3 0x40C94C0 326 327 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_4 0x40C94C4 328 329 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_5 0x40C94C8 330 331 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_6 0x40C94CC 332 333 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_7 0x40C94D0 334 335 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_8 0x40C94D4 336 337 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_9 0x40C94D8 338 339 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_10 0x40C94DC 340 341 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_11 0x40C94E0 342 343 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_12 0x40C94E4 344 345 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_13 0x40C94E8 346 347 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_14 0x40C94EC 348 349 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_15 0x40C94F0 350 351 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_16 0x40C94F4 352 353 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_17 0x40C94F8 354 355 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_18 0x40C94FC 356 357 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_19 0x40C9500 358 359 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_20 0x40C9504 360 361 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_21 0x40C9508 362 363 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_22 0x40C950C 364 365 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_23 0x40C9510 366 367 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_24 0x40C9514 368 369 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_25 0x40C9518 370 371 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_26 0x40C951C 372 373 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_27 0x40C9520 374 375 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_28 0x40C9524 376 377 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_29 0x40C9528 378 379 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_30 0x40C952C 380 381 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_31 0x40C9530 382 383 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_32 0x40C9534 384 385 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_33 0x40C9538 386 387 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_34 0x40C953C 388 389 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_35 0x40C9540 390 391 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_36 0x40C9544 392 393 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_37 0x40C9548 394 395 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_38 0x40C954C 396 397 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_39 0x40C9550 398 399 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_40 0x40C9554 400 401 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_41 0x40C9558 402 403 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_42 0x40C955C 404 405 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_43 0x40C9560 406 407 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_44 0x40C9564 408 409 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_45 0x40C9568 410 411 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_46 0x40C956C 412 413 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_47 0x40C9570 414 415 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_48 0x40C9574 416 417 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_49 0x40C9578 418 419 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_50 0x40C957C 420 421 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_51 0x40C9580 422 423 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_52 0x40C9584 424 425 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_53 0x40C9588 426 427 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_54 0x40C958C 428 429 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_55 0x40C9590 430 431 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_56 0x40C9594 432 433 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_57 0x40C9598 434 435 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_58 0x40C959C 436 437 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_59 0x40C95A0 438 439 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_60 0x40C95A4 440 441 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_61 0x40C95A8 442 443 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_62 0x40C95AC 444 445 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_63 0x40C95B0 446 447 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_0 0x40C95B4 448 449 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_1 0x40C95B8 450 451 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_2 0x40C95BC 452 453 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_3 0x40C95C0 454 455 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_4 0x40C95C4 456 457 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_5 0x40C95C8 458 459 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_6 0x40C95CC 460 461 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_7 0x40C95D0 462 463 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_8 0x40C95D4 464 465 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_9 0x40C95D8 466 467 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_10 0x40C95DC 468 469 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_11 0x40C95E0 470 471 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_12 0x40C95E4 472 473 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_13 0x40C95E8 474 475 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_14 0x40C95EC 476 477 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_15 0x40C95F0 478 479 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_16 0x40C95F4 480 481 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_17 0x40C95F8 482 483 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_18 0x40C95FC 484 485 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_19 0x40C9600 486 487 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_20 0x40C9604 488 489 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_21 0x40C9608 490 491 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_22 0x40C960C 492 493 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_23 0x40C9610 494 495 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_24 0x40C9614 496 497 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_25 0x40C9618 498 499 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_26 0x40C961C 500 501 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_27 0x40C9620 502 503 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_28 0x40C9624 504 505 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_29 0x40C9628 506 507 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_30 0x40C962C 508 509 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_31 0x40C9630 510 511 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_32 0x40C9634 512 513 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_33 0x40C9638 514 515 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_34 0x40C963C 516 517 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_35 0x40C9640 518 519 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_36 0x40C9644 520 521 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_37 0x40C9648 522 523 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_38 0x40C964C 524 525 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_39 0x40C9650 526 527 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_40 0x40C9654 528 529 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_41 0x40C9658 530 531 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_42 0x40C965C 532 533 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_43 0x40C9660 534 535 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_44 0x40C9664 536 537 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_45 0x40C9668 538 539 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_46 0x40C966C 540 541 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_47 0x40C9670 542 543 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_48 0x40C9674 544 545 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_49 0x40C9678 546 547 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_50 0x40C967C 548 549 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_51 0x40C9680 550 551 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_52 0x40C9684 552 553 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_53 0x40C9688 554 555 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_54 0x40C968C 556 557 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_55 0x40C9690 558 559 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_56 0x40C9694 560 561 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_57 0x40C9698 562 563 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_58 0x40C969C 564 565 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_59 0x40C96A0 566 567 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_60 0x40C96A4 568 569 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_61 0x40C96A8 570 571 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_62 0x40C96AC 572 573 #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63 0x40C96B0 574 575 #endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ */ 576