1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_HMMU0_STLB 19*e65e175bSOded Gabbay * (Prototype: STLB) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_BUSY */ 24*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 25*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID */ 28*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 29*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ 32*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 33*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ 36*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 37*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_CACHE_INV */ 40*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 41*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF 42*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 43*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ 46*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 47*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ 50*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 51*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ 54*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 55*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 56*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 57*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 58*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 59*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 60*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 61*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 62*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 63*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 64*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 65*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 66*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 67*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 68*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 69*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 70*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 71*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ 74*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 75*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF 76*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 77*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 78*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 79*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ 82*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 83*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 84*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 85*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 86*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 87*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 88*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 89*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 90*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 91*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 92*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 93*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 94*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 95*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \ 96*e65e175bSOded Gabbay 0x7E00000 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ 99*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 100*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ 103*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 104*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_ALL_START */ 107*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 108*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_ALL_SET */ 111*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 112*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_PS */ 115*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 116*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ 119*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 120*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ 123*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 124*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_INV_SET */ 127*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 128*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SRAM_INIT */ 131*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 132*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 133*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 134*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC 135*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 136*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ 141*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 142*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 143*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 144*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ 147*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 148*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ 151*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 152*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ 155*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 156*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F 157*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 158*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 159*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 160*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 161*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 162*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ 165*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 166*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF 167*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 168*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 169*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 170*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 171*e65e175bSOded Gabbay 172*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ 173*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 174*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF 175*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 176*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 177*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 178*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 179*e65e175bSOded Gabbay 180*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ 181*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 182*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF 183*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 184*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 185*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 186*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ 189*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 190*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF 191*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 192*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 193*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 194*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ 197*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 198*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF 199*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 200*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 201*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 202*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ 205*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 206*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF 207*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 208*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 209*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 210*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 211*e65e175bSOded Gabbay 212*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ 213*e65e175bSOded Gabbay 214*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ 215*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 216*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 217*e65e175bSOded Gabbay 218*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ 219*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 220*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 221*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 222*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 223*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 224*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 225*e65e175bSOded Gabbay 226*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ 227*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 228*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 229*e65e175bSOded Gabbay 230*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ 231*e65e175bSOded Gabbay #define \ 232*e65e175bSOded Gabbay DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \ 233*e65e175bSOded Gabbay 0 234*e65e175bSOded Gabbay #define \ 235*e65e175bSOded Gabbay DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ 236*e65e175bSOded Gabbay 0x1 237*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 238*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 239*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 240*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC 241*e65e175bSOded Gabbay 242*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ 243*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 244*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF 245*e65e175bSOded Gabbay 246*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ 247*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 248*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF 249*e65e175bSOded Gabbay 250*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ 251*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 252*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF 253*e65e175bSOded Gabbay 254*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ 255*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 256*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF 257*e65e175bSOded Gabbay 258*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ 259*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 260*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 261*e65e175bSOded Gabbay 262*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ 263*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 264*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \ 265*e65e175bSOded Gabbay 0x1FF 266*e65e175bSOded Gabbay 267*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ 268*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 269*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \ 270*e65e175bSOded Gabbay 0x1FF 271*e65e175bSOded Gabbay 272*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ 273*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 274*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \ 275*e65e175bSOded Gabbay 0x1FF 276*e65e175bSOded Gabbay 277*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ 278*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 279*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \ 280*e65e175bSOded Gabbay 0x1FF 281*e65e175bSOded Gabbay 282*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ 283*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 284*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \ 285*e65e175bSOded Gabbay 0x1FF 286*e65e175bSOded Gabbay 287*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ 288*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 289*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \ 290*e65e175bSOded Gabbay 0x1FF 291*e65e175bSOded Gabbay 292*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ 293*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 294*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \ 295*e65e175bSOded Gabbay 0x1FF 296*e65e175bSOded Gabbay 297*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ 298*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 299*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \ 300*e65e175bSOded Gabbay 0x1FF 301*e65e175bSOded Gabbay 302*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ 303*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 304*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \ 305*e65e175bSOded Gabbay 0x1FF 306*e65e175bSOded Gabbay 307*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ 308*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 309*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \ 310*e65e175bSOded Gabbay 0x1FF 311*e65e175bSOded Gabbay 312*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ 313*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 314*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF 315*e65e175bSOded Gabbay 316*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ 317*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 318*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF 319*e65e175bSOded Gabbay 320*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ 321*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 322*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF 323*e65e175bSOded Gabbay 324*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ 325*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 326*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF 327*e65e175bSOded Gabbay 328*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ 329*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 330*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF 331*e65e175bSOded Gabbay 332*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ 333*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 334*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF 335*e65e175bSOded Gabbay 336*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ 337*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 338*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF 339*e65e175bSOded Gabbay 340*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ 341*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 342*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF 343*e65e175bSOded Gabbay 344*e65e175bSOded Gabbay /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ 345*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 346*e65e175bSOded Gabbay #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF 347*e65e175bSOded Gabbay 348*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ 349