1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_HMMU0_MMU 19*e65e175bSOded Gabbay * (Prototype: MMU) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_ENABLE */ 24*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0 25*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_FORCE_ORDERING */ 28*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0 29*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1 30*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1 31*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_FEATURE_ENABLE */ 34*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 35*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 36*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 37*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 38*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 39*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 40*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 41*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 42*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 43*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 44*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 45*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 46*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6 47*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40 48*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7 49*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */ 52*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0 53*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */ 56*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0 57*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */ 60*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0 61*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SCRAMBLER */ 64*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 65*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F 66*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 67*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 68*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 69*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 70*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8 71*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */ 74*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0 75*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3 76*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 77*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 78*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 79*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_SEI_MASK */ 82*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0 83*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */ 86*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0 87*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */ 90*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0 91*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */ 94*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 95*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 96*e65e175bSOded Gabbay 97*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */ 98*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0 99*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 100*e65e175bSOded Gabbay 101*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */ 102*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 103*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */ 106*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0 107*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1 108*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1 109*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_INTERRUPT_CLR */ 112*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0 113*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_INTERRUPT_MASK */ 116*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0 117*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */ 120*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0 121*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */ 124*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0 125*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PIPE_CREDIT */ 128*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0 129*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF 130*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7 131*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80 132*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8 133*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00 134*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15 135*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_BYPASS */ 138*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0 139*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */ 142*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0 143*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF 144*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4 145*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0 146*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8 147*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00 148*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12 149*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000 150*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16 151*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000 152*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20 153*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK \ 154*e65e175bSOded Gabbay 0x100000 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */ 157*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0 158*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF 159*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10 160*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00 161*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20 162*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */ 165*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0 166*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF 167*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9 168*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00 169*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18 170*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000 171*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27 172*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000 173*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28 174*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000 175*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29 176*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */ 179*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18 180*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000 181*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29 182*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000 183*e65e175bSOded Gabbay 184*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */ 185*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0 186*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */ 189*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0 190*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF 191*e65e175bSOded Gabbay 192*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */ 193*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0 194*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */ 197*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0 198*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF 199*e65e175bSOded Gabbay 200*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */ 201*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0 202*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */ 205*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0 206*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF 207*e65e175bSOded Gabbay 208*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */ 209*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0 210*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF 211*e65e175bSOded Gabbay 212*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */ 213*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0 214*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF 215*e65e175bSOded Gabbay 216*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */ 217*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0 218*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF 219*e65e175bSOded Gabbay 220*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */ 221*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0 222*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF 223*e65e175bSOded Gabbay 224*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */ 225*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0 226*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF 227*e65e175bSOded Gabbay 228*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */ 229*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0 230*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF 231*e65e175bSOded Gabbay 232*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */ 233*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0 234*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF 235*e65e175bSOded Gabbay 236*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */ 237*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 238*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK \ 239*e65e175bSOded Gabbay 0xFFFFFFFF 240*e65e175bSOded Gabbay 241*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */ 242*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 243*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK \ 244*e65e175bSOded Gabbay 0xFFFFFFFF 245*e65e175bSOded Gabbay 246*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */ 247*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 248*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK \ 249*e65e175bSOded Gabbay 0xFFFFFFFF 250*e65e175bSOded Gabbay 251*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */ 252*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 253*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK \ 254*e65e175bSOded Gabbay 0xFFFFFFFF 255*e65e175bSOded Gabbay 256*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */ 257*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0 258*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1 259*e65e175bSOded Gabbay 260*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */ 261*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0 262*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF 263*e65e175bSOded Gabbay 264*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */ 265*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0 266*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF 267*e65e175bSOded Gabbay 268*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */ 269*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0 270*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1 271*e65e175bSOded Gabbay 272*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */ 273*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0 274*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF 275*e65e175bSOded Gabbay 276*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */ 277*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0 278*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF 279*e65e175bSOded Gabbay 280*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_SRC_NUM */ 281*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0 282*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1 283*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1 284*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E 285*e65e175bSOded Gabbay 286*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */ 287*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0 288*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF 289*e65e175bSOded Gabbay 290*e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */ 291*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0 292*e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF 293*e65e175bSOded Gabbay 294*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */ 295