1e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2e65e175bSOded Gabbay * 3e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4e65e175bSOded Gabbay * All Rights Reserved. 5e65e175bSOded Gabbay * 6e65e175bSOded Gabbay */ 7e65e175bSOded Gabbay 8e65e175bSOded Gabbay /************************************ 9e65e175bSOded Gabbay ** This is an auto-generated file ** 10e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11e65e175bSOded Gabbay ************************************/ 12e65e175bSOded Gabbay 13e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 14e65e175bSOded Gabbay #define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 15e65e175bSOded Gabbay 16e65e175bSOded Gabbay /* 17e65e175bSOded Gabbay ***************************************** 18e65e175bSOded Gabbay * DCORE0_HMMU0_MMU 19e65e175bSOded Gabbay * (Prototype: MMU) 20e65e175bSOded Gabbay ***************************************** 21e65e175bSOded Gabbay */ 22e65e175bSOded Gabbay 23e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_ENABLE */ 24e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0 25e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1 26e65e175bSOded Gabbay 27e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_FORCE_ORDERING */ 28e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0 29e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1 30e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1 31e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2 32e65e175bSOded Gabbay 33e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_FEATURE_ENABLE */ 34e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 35e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 36e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 37e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 38e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 39e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 40e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 41e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 42e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 43e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 44e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 45e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 46e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6 47e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40 48e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7 49e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80 50e65e175bSOded Gabbay 51e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */ 52e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0 53e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF 54e65e175bSOded Gabbay 55e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */ 56e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0 57e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF 58e65e175bSOded Gabbay 59e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */ 60e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0 61e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF 62e65e175bSOded Gabbay 63e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SCRAMBLER */ 64e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 65e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F 66e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 67e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 68e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 69e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 70e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8 71e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00 72e65e175bSOded Gabbay 73e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */ 74e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0 75e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3 76e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 77e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 78e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 79e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 80e65e175bSOded Gabbay 81e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_SEI_MASK */ 82e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0 83e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF 84e65e175bSOded Gabbay 85e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */ 86e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0 87e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF 88e65e175bSOded Gabbay 89e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */ 90e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0 91e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 92e65e175bSOded Gabbay 93e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */ 94e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 95e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 96e65e175bSOded Gabbay 97e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */ 98e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0 99e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 100e65e175bSOded Gabbay 101e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */ 102e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 103e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 104e65e175bSOded Gabbay 105e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */ 106e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0 107e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1 108e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1 109e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2 110e65e175bSOded Gabbay 111e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_INTERRUPT_CLR */ 112e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0 113e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF 114e65e175bSOded Gabbay 115e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_INTERRUPT_MASK */ 116e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0 117e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF 118e65e175bSOded Gabbay 119e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */ 120e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0 121e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF 122e65e175bSOded Gabbay 123e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */ 124e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0 125e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1 126e65e175bSOded Gabbay 127e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PIPE_CREDIT */ 128e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0 129e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF 130e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7 131e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80 132e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8 133e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00 134e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15 135e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000 136e65e175bSOded Gabbay 137e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_BYPASS */ 138e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0 139e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1 140e65e175bSOded Gabbay 141e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */ 142e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0 143e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF 144e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4 145e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0 146e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8 147e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00 148e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12 149e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000 150e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16 151e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000 152e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20 153*2fd7db3cSOded Gabbay #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK 0x100000 154e65e175bSOded Gabbay 155e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */ 156e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0 157e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF 158e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10 159e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00 160e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20 161e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000 162e65e175bSOded Gabbay 163e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */ 164e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0 165e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF 166e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9 167e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00 168e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18 169e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000 170e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27 171e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000 172e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28 173e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000 174e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29 175e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000 176e65e175bSOded Gabbay 177e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */ 178e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18 179e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000 180e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29 181e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000 182e65e175bSOded Gabbay 183e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */ 184e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0 185e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF 186e65e175bSOded Gabbay 187e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */ 188e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0 189e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF 190e65e175bSOded Gabbay 191e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */ 192e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0 193e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF 194e65e175bSOded Gabbay 195e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */ 196e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0 197e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF 198e65e175bSOded Gabbay 199e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */ 200e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0 201e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1 202e65e175bSOded Gabbay 203e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */ 204e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0 205e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF 206e65e175bSOded Gabbay 207e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */ 208e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0 209e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF 210e65e175bSOded Gabbay 211e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */ 212e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0 213e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF 214e65e175bSOded Gabbay 215e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */ 216e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0 217e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF 218e65e175bSOded Gabbay 219e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */ 220e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0 221e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF 222e65e175bSOded Gabbay 223e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */ 224e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0 225e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF 226e65e175bSOded Gabbay 227e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */ 228e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0 229e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF 230e65e175bSOded Gabbay 231e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */ 232e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0 233e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF 234e65e175bSOded Gabbay 235e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */ 236e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 237*2fd7db3cSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF 238e65e175bSOded Gabbay 239e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */ 240e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 241*2fd7db3cSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF 242e65e175bSOded Gabbay 243e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */ 244e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 245*2fd7db3cSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF 246e65e175bSOded Gabbay 247e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */ 248e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 249*2fd7db3cSOded Gabbay #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF 250e65e175bSOded Gabbay 251e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */ 252e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0 253e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1 254e65e175bSOded Gabbay 255e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */ 256e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0 257e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF 258e65e175bSOded Gabbay 259e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */ 260e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0 261e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF 262e65e175bSOded Gabbay 263e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */ 264e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0 265e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1 266e65e175bSOded Gabbay 267e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */ 268e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0 269e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF 270e65e175bSOded Gabbay 271e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */ 272e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0 273e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF 274e65e175bSOded Gabbay 275e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_MMU_SRC_NUM */ 276e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0 277e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1 278e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1 279e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E 280e65e175bSOded Gabbay 281e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */ 282e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0 283e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF 284e65e175bSOded Gabbay 285e65e175bSOded Gabbay /* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */ 286e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0 287e65e175bSOded Gabbay #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF 288e65e175bSOded Gabbay 289e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */ 290