1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_EDMA0_CORE 19*e65e175bSOded Gabbay * (Prototype: DMA_CORE) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_CFG_0 */ 24*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0 25*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_CFG_1 */ 28*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0 29*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1 30*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1 31*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_PROT */ 34*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0 35*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1 36*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1 37*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_CKG */ 40*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 41*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 42*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 43*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 44*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2 45*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_GLBL */ 48*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 49*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 50*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 51*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 52*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 53*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */ 56*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 57*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */ 60*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 61*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF 62*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 63*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */ 66*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 67*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */ 70*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 71*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */ 74*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 75*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF 76*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 77*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 78*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 79*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */ 82*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 83*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */ 86*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 87*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF 88*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 89*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */ 92*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 93*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */ 96*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 97*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */ 100*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 101*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF 102*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 103*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 104*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 105*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */ 108*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 109*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF 110*e65e175bSOded Gabbay 111*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */ 112*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 113*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */ 116*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 117*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */ 120*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 121*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 122*e65e175bSOded Gabbay 123*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */ 124*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 125*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF 126*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 127*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 128*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 129*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 130*e65e175bSOded Gabbay 131*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */ 132*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 133*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */ 136*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 137*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F 138*e65e175bSOded Gabbay 139*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */ 140*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 141*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF 142*e65e175bSOded Gabbay 143*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */ 144*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 145*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */ 148*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 149*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF 150*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 151*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 152*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 153*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 154*e65e175bSOded Gabbay 155*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */ 156*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 157*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F 158*e65e175bSOded Gabbay 159*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */ 160*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 161*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF 162*e65e175bSOded Gabbay 163*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_ERR_CFG */ 164*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 165*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 166*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 167*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 168*e65e175bSOded Gabbay 169*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_ERR_CAUSE */ 170*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 171*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 172*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 173*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 174*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 175*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 176*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 177*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 178*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 179*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 180*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 181*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 182*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 183*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 184*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 185*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */ 188*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 189*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */ 192*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 193*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF 194*e65e175bSOded Gabbay 195*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_ERRMSG_WDATA */ 196*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 197*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF 198*e65e175bSOded Gabbay 199*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS0 */ 200*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 201*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF 202*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 203*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 204*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT 31 205*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS0_BUSY_MASK 0x80000000 206*e65e175bSOded Gabbay 207*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS1 */ 208*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT 0 209*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1 210*e65e175bSOded Gabbay 211*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */ 212*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 213*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 214*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 215*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */ 218*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 219*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */ 222*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 223*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF 224*e65e175bSOded Gabbay 225*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */ 226*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 227*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */ 230*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 231*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF 232*e65e175bSOded Gabbay 233*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ 234*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 235*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF 236*e65e175bSOded Gabbay 237*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ 238*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 239*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF 240*e65e175bSOded Gabbay 241*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */ 242*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 243*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF 244*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 245*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 246*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 247*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 248*e65e175bSOded Gabbay 249*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */ 250*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 251*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 252*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 253*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 254*e65e175bSOded Gabbay 255*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */ 256*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 257*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF 258*e65e175bSOded Gabbay 259*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */ 260*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 261*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF 262*e65e175bSOded Gabbay 263*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */ 264*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 265*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF 266*e65e175bSOded Gabbay 267*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */ 268*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 269*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF 270*e65e175bSOded Gabbay 271*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ 272*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 273*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF 274*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 275*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 276*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 277*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 278*e65e175bSOded Gabbay 279*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ 280*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 281*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF 282*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 283*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 284*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 285*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 286*e65e175bSOded Gabbay 287*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */ 288*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 289*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF 290*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 291*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 292*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 293*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 294*e65e175bSOded Gabbay 295*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_PWRLP_CFG */ 296*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 297*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 298*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 299*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 300*e65e175bSOded Gabbay 301*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_PWRLP_STS */ 302*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 303*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F 304*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 305*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 306*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 307*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 308*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 309*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 310*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 311*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 312*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 313*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 314*e65e175bSOded Gabbay 315*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_DESC_CNT */ 316*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 317*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF 318*e65e175bSOded Gabbay 319*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_STS */ 320*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 321*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 322*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 323*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 324*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 325*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 326*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 327*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 328*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 329*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 330*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 331*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 332*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 333*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 334*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 335*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 336*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 337*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 338*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 339*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 340*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 341*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 342*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 343*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 344*e65e175bSOded Gabbay 345*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_BUF_STS */ 346*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 347*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF 348*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 349*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 350*e65e175bSOded Gabbay 351*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */ 352*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 353*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF 354*e65e175bSOded Gabbay 355*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */ 356*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 357*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF 358*e65e175bSOded Gabbay 359*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */ 360*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 361*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF 362*e65e175bSOded Gabbay 363*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */ 364*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 365*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF 366*e65e175bSOded Gabbay 367*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */ 368*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 369*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF 370*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 371*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 372*e65e175bSOded Gabbay 373*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */ 374*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 375*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 376*e65e175bSOded Gabbay 377*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_L2H_CMPR_LO */ 378*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 379*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 380*e65e175bSOded Gabbay 381*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_L2H_CMPR_HI */ 382*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 383*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF 384*e65e175bSOded Gabbay 385*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_L2H_MASK_LO */ 386*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 387*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 388*e65e175bSOded Gabbay 389*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_L2H_MASK_HI */ 390*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 391*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF 392*e65e175bSOded Gabbay 393*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_IDLE_IND_MASK */ 394*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 395*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 396*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 397*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 398*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 399*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 400*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 401*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 402*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 403*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 404*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 405*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 406*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 407*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 408*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 409*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 410*e65e175bSOded Gabbay 411*e65e175bSOded Gabbay /* DCORE0_EDMA0_CORE_APB_ENABLER */ 412*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 413*e65e175bSOded Gabbay #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 414*e65e175bSOded Gabbay 415*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */ 416