1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DCORE0_EDMA0_CORE_CTX 19*e65e175bSOded Gabbay * (Prototype: DMA_CORE_CTX) 20*e65e175bSOded Gabbay ***************************************** 21*e65e175bSOded Gabbay */ 22*e65e175bSOded Gabbay 23*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864 26*e65e175bSOded Gabbay 27*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C 30*e65e175bSOded Gabbay 31*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870 32*e65e175bSOded Gabbay 33*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874 34*e65e175bSOded Gabbay 35*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878 36*e65e175bSOded Gabbay 37*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884 42*e65e175bSOded Gabbay 43*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C 46*e65e175bSOded Gabbay 47*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898 52*e65e175bSOded Gabbay 53*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0 56*e65e175bSOded Gabbay 57*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4 58*e65e175bSOded Gabbay 59*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC 62*e65e175bSOded Gabbay 63*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4 66*e65e175bSOded Gabbay 67*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4 74*e65e175bSOded Gabbay 75*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC 78*e65e175bSOded Gabbay 79*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8 84*e65e175bSOded Gabbay 85*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC 86*e65e175bSOded Gabbay 87*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0 88*e65e175bSOded Gabbay 89*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4 90*e65e175bSOded Gabbay 91*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC 94*e65e175bSOded Gabbay 95*e65e175bSOded Gabbay #endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */ 96