1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2019-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef GAUDI_REG_MAP_H_ 9*e65e175bSOded Gabbay #define GAUDI_REG_MAP_H_ 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay /* 12*e65e175bSOded Gabbay * PSOC scratch-pad registers 13*e65e175bSOded Gabbay */ 14*e65e175bSOded Gabbay #define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 15*e65e175bSOded Gabbay #define mmGIC_HOST_PI_UPD_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 16*e65e175bSOded Gabbay #define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 17*e65e175bSOded Gabbay #define mmGIC_MME_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 18*e65e175bSOded Gabbay #define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 19*e65e175bSOded Gabbay #define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 20*e65e175bSOded Gabbay #define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 21*e65e175bSOded Gabbay #define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 22*e65e175bSOded Gabbay #define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 23*e65e175bSOded Gabbay #define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 24*e65e175bSOded Gabbay #define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 25*e65e175bSOded Gabbay #define mmFUSE_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 26*e65e175bSOded Gabbay #define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 27*e65e175bSOded Gabbay #define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 28*e65e175bSOded Gabbay #define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 29*e65e175bSOded Gabbay #define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 30*e65e175bSOded Gabbay #define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 31*e65e175bSOded Gabbay #define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 32*e65e175bSOded Gabbay #define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 33*e65e175bSOded Gabbay #define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 34*e65e175bSOded Gabbay #define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 35*e65e175bSOded Gabbay #define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 36*e65e175bSOded Gabbay #define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 37*e65e175bSOded Gabbay #define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #endif /* GAUDI_REG_MAP_H_ */ 40