1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2020 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef GAUDI_MASKS_H_ 9*e65e175bSOded Gabbay #define GAUDI_MASKS_H_ 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay #include "asic_reg/gaudi_regs.h" 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay /* Useful masks for bits in various registers */ 14*e65e175bSOded Gabbay #define PCI_DMA_QMAN_ENABLE (\ 15*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 16*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ 17*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF))) 18*e65e175bSOded Gabbay 19*e65e175bSOded Gabbay #define QMAN_EXTERNAL_MAKE_TRUSTED (\ 20*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 21*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \ 22*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \ 23*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define QMAN_INTERNAL_MAKE_TRUSTED (\ 26*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 27*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 28*e65e175bSOded Gabbay 29*e65e175bSOded Gabbay #define HBM_DMA_QMAN_ENABLE (\ 30*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 31*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 32*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define QMAN_MME_ENABLE (\ 35*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 36*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 37*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define QMAN_TPC_ENABLE (\ 40*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 41*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \ 42*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F))) 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define NIC_QMAN_ENABLE (\ 45*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 46*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ 47*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_CFG0_CP_EN_MASK, 0xF))) 48*e65e175bSOded Gabbay 49*e65e175bSOded Gabbay #define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ 50*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ 51*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ 52*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \ 53*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) 54*e65e175bSOded Gabbay 55*e65e175bSOded Gabbay #define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ 56*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \ 57*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \ 58*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \ 59*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1))) 60*e65e175bSOded Gabbay 61*e65e175bSOded Gabbay #define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 62*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 63*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ 64*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 67*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 68*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ 69*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \ 70*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 73*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 74*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 75*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 76*e65e175bSOded Gabbay 77*e65e175bSOded Gabbay #define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 78*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 79*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 80*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ 81*e65e175bSOded Gabbay (FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) 82*e65e175bSOded Gabbay 83*e65e175bSOded Gabbay #define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 84*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 85*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 86*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 89*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 90*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 91*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ 92*e65e175bSOded Gabbay (FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 95*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 96*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \ 97*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F))) 98*e65e175bSOded Gabbay 99*e65e175bSOded Gabbay #define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 100*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 101*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \ 102*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)) | \ 103*e65e175bSOded Gabbay (FIELD_PREP(MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) 104*e65e175bSOded Gabbay 105*e65e175bSOded Gabbay #define NIC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ 106*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \ 107*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \ 108*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF))) 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define NIC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ 111*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \ 112*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \ 113*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)) | \ 114*e65e175bSOded Gabbay (FIELD_PREP(NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK, 0x1))) 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define QMAN_CGM1_PWR_GATE_EN (FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA)) 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay /* RESET registers configuration */ 119*e65e175bSOded Gabbay #define CFG_RST_L_PSOC_MASK BIT_MASK(0) 120*e65e175bSOded Gabbay #define CFG_RST_L_PCIE_MASK BIT_MASK(1) 121*e65e175bSOded Gabbay #define CFG_RST_L_PCIE_IF_MASK BIT_MASK(2) 122*e65e175bSOded Gabbay #define CFG_RST_L_HBM_S_PLL_MASK BIT_MASK(3) 123*e65e175bSOded Gabbay #define CFG_RST_L_TPC_S_PLL_MASK BIT_MASK(4) 124*e65e175bSOded Gabbay #define CFG_RST_L_MME_S_PLL_MASK BIT_MASK(5) 125*e65e175bSOded Gabbay #define CFG_RST_L_CPU_PLL_MASK BIT_MASK(6) 126*e65e175bSOded Gabbay #define CFG_RST_L_PCIE_PLL_MASK BIT_MASK(7) 127*e65e175bSOded Gabbay #define CFG_RST_L_NIC_S_PLL_MASK BIT_MASK(8) 128*e65e175bSOded Gabbay #define CFG_RST_L_HBM_N_PLL_MASK BIT_MASK(9) 129*e65e175bSOded Gabbay #define CFG_RST_L_TPC_N_PLL_MASK BIT_MASK(10) 130*e65e175bSOded Gabbay #define CFG_RST_L_MME_N_PLL_MASK BIT_MASK(11) 131*e65e175bSOded Gabbay #define CFG_RST_L_NIC_N_PLL_MASK BIT_MASK(12) 132*e65e175bSOded Gabbay #define CFG_RST_L_DMA_W_PLL_MASK BIT_MASK(13) 133*e65e175bSOded Gabbay #define CFG_RST_L_SIF_W_PLL_MASK BIT_MASK(14) 134*e65e175bSOded Gabbay #define CFG_RST_L_MESH_W_PLL_MASK BIT_MASK(15) 135*e65e175bSOded Gabbay #define CFG_RST_L_SRAM_W_PLL_MASK BIT_MASK(16) 136*e65e175bSOded Gabbay #define CFG_RST_L_DMA_E_PLL_MASK BIT_MASK(17) 137*e65e175bSOded Gabbay #define CFG_RST_L_SIF_E_PLL_MASK BIT_MASK(18) 138*e65e175bSOded Gabbay #define CFG_RST_L_MESH_E_PLL_MASK BIT_MASK(19) 139*e65e175bSOded Gabbay #define CFG_RST_L_SRAM_E_PLL_MASK BIT_MASK(20) 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define CFG_RST_L_IF_1_MASK BIT_MASK(21) 142*e65e175bSOded Gabbay #define CFG_RST_L_IF_0_MASK BIT_MASK(22) 143*e65e175bSOded Gabbay #define CFG_RST_L_IF_2_MASK BIT_MASK(23) 144*e65e175bSOded Gabbay #define CFG_RST_L_IF_3_MASK BIT_MASK(24) 145*e65e175bSOded Gabbay #define CFG_RST_L_IF_MASK GENMASK(24, 21) 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define CFG_RST_L_TPC_0_MASK BIT_MASK(25) 148*e65e175bSOded Gabbay #define CFG_RST_L_TPC_1_MASK BIT_MASK(26) 149*e65e175bSOded Gabbay #define CFG_RST_L_TPC_2_MASK BIT_MASK(27) 150*e65e175bSOded Gabbay #define CFG_RST_L_TPC_3_MASK BIT_MASK(28) 151*e65e175bSOded Gabbay #define CFG_RST_L_TPC_4_MASK BIT_MASK(29) 152*e65e175bSOded Gabbay #define CFG_RST_L_TPC_5_MASK BIT_MASK(30) 153*e65e175bSOded Gabbay #define CFG_RST_L_TPC_6_MASK BIT_MASK(31) 154*e65e175bSOded Gabbay #define CFG_RST_L_TPC_MASK GENMASK(31, 25) 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #define CFG_RST_H_TPC_7_MASK BIT_MASK(0) 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay #define CFG_RST_H_MME_0_MASK BIT_MASK(1) 159*e65e175bSOded Gabbay #define CFG_RST_H_MME_1_MASK BIT_MASK(2) 160*e65e175bSOded Gabbay #define CFG_RST_H_MME_2_MASK BIT_MASK(3) 161*e65e175bSOded Gabbay #define CFG_RST_H_MME_3_MASK BIT_MASK(4) 162*e65e175bSOded Gabbay #define CFG_RST_H_MME_MASK GENMASK(4, 1) 163*e65e175bSOded Gabbay 164*e65e175bSOded Gabbay #define CFG_RST_H_HBM_0_MASK BIT_MASK(5) 165*e65e175bSOded Gabbay #define CFG_RST_H_HBM_1_MASK BIT_MASK(6) 166*e65e175bSOded Gabbay #define CFG_RST_H_HBM_2_MASK BIT_MASK(7) 167*e65e175bSOded Gabbay #define CFG_RST_H_HBM_3_MASK BIT_MASK(8) 168*e65e175bSOded Gabbay #define CFG_RST_H_HBM_MASK GENMASK(8, 5) 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay #define CFG_RST_H_NIC_0_MASK BIT_MASK(9) 171*e65e175bSOded Gabbay #define CFG_RST_H_NIC_1_MASK BIT_MASK(10) 172*e65e175bSOded Gabbay #define CFG_RST_H_NIC_2_MASK BIT_MASK(11) 173*e65e175bSOded Gabbay #define CFG_RST_H_NIC_3_MASK BIT_MASK(12) 174*e65e175bSOded Gabbay #define CFG_RST_H_NIC_4_MASK BIT_MASK(13) 175*e65e175bSOded Gabbay #define CFG_RST_H_NIC_MASK GENMASK(13, 9) 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define CFG_RST_H_SM_0_MASK BIT_MASK(14) 178*e65e175bSOded Gabbay #define CFG_RST_H_SM_1_MASK BIT_MASK(15) 179*e65e175bSOded Gabbay #define CFG_RST_H_SM_2_MASK BIT_MASK(16) 180*e65e175bSOded Gabbay #define CFG_RST_H_SM_3_MASK BIT_MASK(17) 181*e65e175bSOded Gabbay #define CFG_RST_H_SM_MASK GENMASK(17, 14) 182*e65e175bSOded Gabbay 183*e65e175bSOded Gabbay #define CFG_RST_H_DMA_0_MASK BIT_MASK(18) 184*e65e175bSOded Gabbay #define CFG_RST_H_DMA_1_MASK BIT_MASK(19) 185*e65e175bSOded Gabbay #define CFG_RST_H_DMA_MASK GENMASK(19, 18) 186*e65e175bSOded Gabbay 187*e65e175bSOded Gabbay #define CFG_RST_H_CPU_MASK BIT_MASK(20) 188*e65e175bSOded Gabbay #define CFG_RST_H_MMU_MASK BIT_MASK(21) 189*e65e175bSOded Gabbay 190*e65e175bSOded Gabbay #define UNIT_RST_L_PSOC_SHIFT 0 191*e65e175bSOded Gabbay #define UNIT_RST_L_PCIE_SHIFT 1 192*e65e175bSOded Gabbay #define UNIT_RST_L_PCIE_IF_SHIFT 2 193*e65e175bSOded Gabbay #define UNIT_RST_L_HBM_S_PLL_SHIFT 3 194*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_S_PLL_SHIFT 4 195*e65e175bSOded Gabbay #define UNIT_RST_L_MME_S_PLL_SHIFT 5 196*e65e175bSOded Gabbay #define UNIT_RST_L_CPU_PLL_SHIFT 6 197*e65e175bSOded Gabbay #define UNIT_RST_L_PCIE_PLL_SHIFT 7 198*e65e175bSOded Gabbay #define UNIT_RST_L_NIC_S_PLL_SHIFT 8 199*e65e175bSOded Gabbay #define UNIT_RST_L_HBM_N_PLL_SHIFT 9 200*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_N_PLL_SHIFT 10 201*e65e175bSOded Gabbay #define UNIT_RST_L_MME_N_PLL_SHIFT 11 202*e65e175bSOded Gabbay #define UNIT_RST_L_NIC_N_PLL_SHIFT 12 203*e65e175bSOded Gabbay #define UNIT_RST_L_DMA_W_PLL_SHIFT 13 204*e65e175bSOded Gabbay #define UNIT_RST_L_SIF_W_PLL_SHIFT 14 205*e65e175bSOded Gabbay #define UNIT_RST_L_MESH_W_PLL_SHIFT 15 206*e65e175bSOded Gabbay #define UNIT_RST_L_SRAM_W_PLL_SHIFT 16 207*e65e175bSOded Gabbay #define UNIT_RST_L_DMA_E_PLL_SHIFT 17 208*e65e175bSOded Gabbay #define UNIT_RST_L_SIF_E_PLL_SHIFT 18 209*e65e175bSOded Gabbay #define UNIT_RST_L_MESH_E_PLL_SHIFT 19 210*e65e175bSOded Gabbay #define UNIT_RST_L_SRAM_E_PLL_SHIFT 20 211*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_0_SHIFT 21 212*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_1_SHIFT 22 213*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_2_SHIFT 23 214*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_3_SHIFT 24 215*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_4_SHIFT 25 216*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_5_SHIFT 26 217*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_6_SHIFT 27 218*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_7_SHIFT 28 219*e65e175bSOded Gabbay #define UNIT_RST_L_MME_0_SHIFT 29 220*e65e175bSOded Gabbay #define UNIT_RST_L_MME_1_SHIFT 30 221*e65e175bSOded Gabbay #define UNIT_RST_L_MME_2_SHIFT 31 222*e65e175bSOded Gabbay 223*e65e175bSOded Gabbay #define UNIT_RST_H_MME_3_SHIFT 0 224*e65e175bSOded Gabbay #define UNIT_RST_H_HBM_0_SHIFT 1 225*e65e175bSOded Gabbay #define UNIT_RST_H_HBM_1_SHIFT 2 226*e65e175bSOded Gabbay #define UNIT_RST_H_HBM_2_SHIFT 3 227*e65e175bSOded Gabbay #define UNIT_RST_H_HBM_3_SHIFT 4 228*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_0_SHIFT 5 229*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_1_SHIFT 6 230*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_2_SHIFT 7 231*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_3_SHIFT 8 232*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_4_SHIFT 9 233*e65e175bSOded Gabbay #define UNIT_RST_H_SM_0_SHIFT 10 234*e65e175bSOded Gabbay #define UNIT_RST_H_SM_1_SHIFT 11 235*e65e175bSOded Gabbay #define UNIT_RST_H_SM_2_SHIFT 12 236*e65e175bSOded Gabbay #define UNIT_RST_H_SM_3_SHIFT 13 237*e65e175bSOded Gabbay #define UNIT_RST_H_IF_0_SHIFT 14 238*e65e175bSOded Gabbay #define UNIT_RST_H_IF_1_SHIFT 15 239*e65e175bSOded Gabbay #define UNIT_RST_H_IF_2_SHIFT 16 240*e65e175bSOded Gabbay #define UNIT_RST_H_IF_3_SHIFT 17 241*e65e175bSOded Gabbay #define UNIT_RST_H_DMA_0_SHIFT 18 242*e65e175bSOded Gabbay #define UNIT_RST_H_DMA_1_SHIFT 19 243*e65e175bSOded Gabbay #define UNIT_RST_H_CPU_SHIFT 20 244*e65e175bSOded Gabbay #define UNIT_RST_H_MMU_SHIFT 21 245*e65e175bSOded Gabbay 246*e65e175bSOded Gabbay #define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \ 247*e65e175bSOded Gabbay (1 << UNIT_RST_H_HBM_1_SHIFT) | \ 248*e65e175bSOded Gabbay (1 << UNIT_RST_H_HBM_2_SHIFT) | \ 249*e65e175bSOded Gabbay (1 << UNIT_RST_H_HBM_3_SHIFT)) 250*e65e175bSOded Gabbay 251*e65e175bSOded Gabbay #define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \ 252*e65e175bSOded Gabbay (1 << UNIT_RST_H_NIC_1_SHIFT) | \ 253*e65e175bSOded Gabbay (1 << UNIT_RST_H_NIC_2_SHIFT) | \ 254*e65e175bSOded Gabbay (1 << UNIT_RST_H_NIC_3_SHIFT) | \ 255*e65e175bSOded Gabbay (1 << UNIT_RST_H_NIC_4_SHIFT)) 256*e65e175bSOded Gabbay 257*e65e175bSOded Gabbay #define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \ 258*e65e175bSOded Gabbay (1 << UNIT_RST_H_SM_1_SHIFT) | \ 259*e65e175bSOded Gabbay (1 << UNIT_RST_H_SM_2_SHIFT) | \ 260*e65e175bSOded Gabbay (1 << UNIT_RST_H_SM_3_SHIFT)) 261*e65e175bSOded Gabbay 262*e65e175bSOded Gabbay #define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \ 263*e65e175bSOded Gabbay (1 << UNIT_RST_H_MME_1_SHIFT) | \ 264*e65e175bSOded Gabbay (1 << UNIT_RST_H_MME_2_SHIFT)) 265*e65e175bSOded Gabbay 266*e65e175bSOded Gabbay #define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT) 267*e65e175bSOded Gabbay 268*e65e175bSOded Gabbay #define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \ 269*e65e175bSOded Gabbay (1 << UNIT_RST_L_IF_1_SHIFT) | \ 270*e65e175bSOded Gabbay (1 << UNIT_RST_L_IF_2_SHIFT) | \ 271*e65e175bSOded Gabbay (1 << UNIT_RST_L_IF_3_SHIFT)) 272*e65e175bSOded Gabbay 273*e65e175bSOded Gabbay #define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \ 274*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_1_SHIFT) | \ 275*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_2_SHIFT) | \ 276*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_3_SHIFT) | \ 277*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_4_SHIFT) | \ 278*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_5_SHIFT) | \ 279*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_6_SHIFT) | \ 280*e65e175bSOded Gabbay (1 << UNIT_RST_L_TPC_7_SHIFT)) 281*e65e175bSOded Gabbay 282*e65e175bSOded Gabbay /* CPU_CA53_CFG_ARM_RST_CONTROL */ 283*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 284*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 285*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 286*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 287*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 288*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 289*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 290*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 291*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 292*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 293*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 294*e65e175bSOded Gabbay #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 295*e65e175bSOded Gabbay 296*e65e175bSOded Gabbay #define CPU_RESET_ASSERT (\ 297*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 298*e65e175bSOded Gabbay 299*e65e175bSOded Gabbay #define CPU_RESET_CORE0_DEASSERT (\ 300*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ 301*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ 302*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ 303*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 304*e65e175bSOded Gabbay 305*e65e175bSOded Gabbay /* QM_IDLE_MASK is valid for all engines QM idle check */ 306*e65e175bSOded Gabbay #define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ 307*e65e175bSOded Gabbay DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ 308*e65e175bSOded Gabbay DMA0_QM_GLBL_STS0_CP_IDLE_MASK) 309*e65e175bSOded Gabbay 310*e65e175bSOded Gabbay /* CGM_IDLE_MASK is valid for all engines CGM idle check */ 311*e65e175bSOded Gabbay #define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK 312*e65e175bSOded Gabbay 313*e65e175bSOded Gabbay #define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \ 314*e65e175bSOded Gabbay (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \ 315*e65e175bSOded Gabbay (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \ 316*e65e175bSOded Gabbay (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \ 317*e65e175bSOded Gabbay (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \ 318*e65e175bSOded Gabbay (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT)) 319*e65e175bSOded Gabbay 320*e65e175bSOded Gabbay #define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 321*e65e175bSOded Gabbay #define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 322*e65e175bSOded Gabbay #define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000 323*e65e175bSOded Gabbay 324*e65e175bSOded Gabbay #define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \ 325*e65e175bSOded Gabbay MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \ 326*e65e175bSOded Gabbay MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK) 327*e65e175bSOded Gabbay 328*e65e175bSOded Gabbay #define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \ 329*e65e175bSOded Gabbay ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \ 330*e65e175bSOded Gabbay (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK)) 331*e65e175bSOded Gabbay 332*e65e175bSOded Gabbay #define IS_DMA_IDLE(dma_core_sts0) \ 333*e65e175bSOded Gabbay !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK) 334*e65e175bSOded Gabbay 335*e65e175bSOded Gabbay #define IS_TPC_IDLE(tpc_cfg_sts) \ 336*e65e175bSOded Gabbay (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK) 337*e65e175bSOded Gabbay 338*e65e175bSOded Gabbay #define IS_MME_IDLE(mme_arch_sts) \ 339*e65e175bSOded Gabbay (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) 340*e65e175bSOded Gabbay 341*e65e175bSOded Gabbay enum axi_id { 342*e65e175bSOded Gabbay AXI_ID_MME, 343*e65e175bSOded Gabbay AXI_ID_TPC, 344*e65e175bSOded Gabbay AXI_ID_DMA, 345*e65e175bSOded Gabbay AXI_ID_NIC, /* Local NIC */ 346*e65e175bSOded Gabbay AXI_ID_PCI, 347*e65e175bSOded Gabbay AXI_ID_CPU, 348*e65e175bSOded Gabbay AXI_ID_PSOC, 349*e65e175bSOded Gabbay AXI_ID_MMU, 350*e65e175bSOded Gabbay AXI_ID_NIC_FT /* Feed-Through NIC */ 351*e65e175bSOded Gabbay }; 352*e65e175bSOded Gabbay 353*e65e175bSOded Gabbay /* RAZWI initiator ID is built from the location in the chip and the AXI ID */ 354*e65e175bSOded Gabbay 355*e65e175bSOded Gabbay #define RAZWI_INITIATOR_AXI_ID_SHIFT 20 356*e65e175bSOded Gabbay #define RAZWI_INITIATOR_AXI_ID_MASK 0xF 357*e65e175bSOded Gabbay #define RAZWI_INITIATOR_X_SHIFT 24 358*e65e175bSOded Gabbay #define RAZWI_INITIATOR_X_MASK 0xF 359*e65e175bSOded Gabbay #define RAZWI_INITIATOR_Y_SHIFT 28 360*e65e175bSOded Gabbay #define RAZWI_INITIATOR_Y_MASK 0x7 361*e65e175bSOded Gabbay 362*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \ 363*e65e175bSOded Gabbay (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \ 364*e65e175bSOded Gabbay RAZWI_INITIATOR_AXI_ID_SHIFT) 365*e65e175bSOded Gabbay 366*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y(x, y) \ 367*e65e175bSOded Gabbay ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ 368*e65e175bSOded Gabbay (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) 369*e65e175bSOded Gabbay 370*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 1) 371*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 1) 372*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 1) 373*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 1) 374*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 1) 375*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 1) 376*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 1) 377*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \ 378*e65e175bSOded Gabbay RAZWI_INITIATOR_ID_X_Y(8, 1) 379*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1) 380*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1) 381*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2) 382*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2) 383*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3) 384*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3) 385*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4) 386*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4) 387*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 6) 388*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 6) 389*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 6) 390*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 6) 391*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 6) 392*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 6) 393*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 6) 394*e65e175bSOded Gabbay #define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 6) 395*e65e175bSOded Gabbay 396*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 397*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 398*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 399*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 400*e65e175bSOded Gabbay 401*e65e175bSOded Gabbay /* STLB_CACHE_INV */ 402*e65e175bSOded Gabbay #define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 403*e65e175bSOded Gabbay #define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF 404*e65e175bSOded Gabbay #define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 405*e65e175bSOded Gabbay #define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 406*e65e175bSOded Gabbay 407*e65e175bSOded Gabbay #define MME_ACC_ACC_STALL_R_SHIFT 0 408*e65e175bSOded Gabbay #define MME_SBAB_SB_STALL_R_SHIFT 0 409*e65e175bSOded Gabbay 410*e65e175bSOded Gabbay #define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700 411*e65e175bSOded Gabbay #define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000 412*e65e175bSOded Gabbay 413*e65e175bSOded Gabbay #define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0 414*e65e175bSOded Gabbay #define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0 415*e65e175bSOded Gabbay 416*e65e175bSOded Gabbay /* DMA_IF_HBM_CRED_EN */ 417*e65e175bSOded Gabbay #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0 418*e65e175bSOded Gabbay #define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1 419*e65e175bSOded Gabbay #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1 420*e65e175bSOded Gabbay #define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2 421*e65e175bSOded Gabbay 422*e65e175bSOded Gabbay #define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0 423*e65e175bSOded Gabbay #define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0 424*e65e175bSOded Gabbay #define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0 425*e65e175bSOded Gabbay #define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0 426*e65e175bSOded Gabbay 427*e65e175bSOded Gabbay #define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0 428*e65e175bSOded Gabbay #define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0 429*e65e175bSOded Gabbay 430*e65e175bSOded Gabbay #define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0 431*e65e175bSOded Gabbay #define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0 432*e65e175bSOded Gabbay 433*e65e175bSOded Gabbay /* MMU_UP_PAGE_ERROR_CAPTURE */ 434*e65e175bSOded Gabbay #define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 435*e65e175bSOded Gabbay #define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 436*e65e175bSOded Gabbay 437*e65e175bSOded Gabbay /* MMU_UP_ACCESS_ERROR_CAPTURE */ 438*e65e175bSOded Gabbay #define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 439*e65e175bSOded Gabbay #define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 440*e65e175bSOded Gabbay 441*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 442*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 443*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 444*e65e175bSOded Gabbay 445*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_MASK (\ 446*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ 447*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ 448*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) 449*e65e175bSOded Gabbay 450*e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 451*e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 452*e65e175bSOded Gabbay 453*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_SHIFT 0 454*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_VALID_MASK 0x1 455*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_SHIFT 1 456*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0_PENDING_MASK 0x1FE 457*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_SHIFT 0 458*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SID_MASK 0xFF 459*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_SHIFT 8 460*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_MASK_MASK 0xFF00 461*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_SHIFT 16 462*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOP_MASK 0x10000 463*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_SHIFT 17 464*e65e175bSOded Gabbay #define SYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0_SOD_MASK 0xFFFE0000 465*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_0_FENCE_ID_SHIFT 20 466*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_0_FENCE_ID_MASK 0x300000 467*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_SHIFT 22 468*e65e175bSOded Gabbay #define TPC0_QM_CP_STS_0_FENCE_IN_PROGRESS_MASK 0x400000 469*e65e175bSOded Gabbay 470*e65e175bSOded Gabbay #endif /* GAUDI_MASKS_H_ */ 471