1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_TPC5_QM_REGS_H_ 14 #define ASIC_REG_TPC5_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * TPC5_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 #define mmTPC5_QM_GLBL_CFG0 0xF48000 23 24 #define mmTPC5_QM_GLBL_CFG1 0xF48004 25 26 #define mmTPC5_QM_GLBL_PROT 0xF48008 27 28 #define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C 29 30 #define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010 31 32 #define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014 33 34 #define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018 35 36 #define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C 37 38 #define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020 39 40 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024 41 42 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028 43 44 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C 45 46 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030 47 48 #define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034 49 50 #define mmTPC5_QM_GLBL_STS0 0xF48038 51 52 #define mmTPC5_QM_GLBL_STS1_0 0xF48040 53 54 #define mmTPC5_QM_GLBL_STS1_1 0xF48044 55 56 #define mmTPC5_QM_GLBL_STS1_2 0xF48048 57 58 #define mmTPC5_QM_GLBL_STS1_3 0xF4804C 59 60 #define mmTPC5_QM_GLBL_STS1_4 0xF48050 61 62 #define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054 63 64 #define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058 65 66 #define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C 67 68 #define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060 69 70 #define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068 71 72 #define mmTPC5_QM_PQ_BASE_LO_0 0xF48070 73 74 #define mmTPC5_QM_PQ_BASE_LO_1 0xF48074 75 76 #define mmTPC5_QM_PQ_BASE_LO_2 0xF48078 77 78 #define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C 79 80 #define mmTPC5_QM_PQ_BASE_HI_0 0xF48080 81 82 #define mmTPC5_QM_PQ_BASE_HI_1 0xF48084 83 84 #define mmTPC5_QM_PQ_BASE_HI_2 0xF48088 85 86 #define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C 87 88 #define mmTPC5_QM_PQ_SIZE_0 0xF48090 89 90 #define mmTPC5_QM_PQ_SIZE_1 0xF48094 91 92 #define mmTPC5_QM_PQ_SIZE_2 0xF48098 93 94 #define mmTPC5_QM_PQ_SIZE_3 0xF4809C 95 96 #define mmTPC5_QM_PQ_PI_0 0xF480A0 97 98 #define mmTPC5_QM_PQ_PI_1 0xF480A4 99 100 #define mmTPC5_QM_PQ_PI_2 0xF480A8 101 102 #define mmTPC5_QM_PQ_PI_3 0xF480AC 103 104 #define mmTPC5_QM_PQ_CI_0 0xF480B0 105 106 #define mmTPC5_QM_PQ_CI_1 0xF480B4 107 108 #define mmTPC5_QM_PQ_CI_2 0xF480B8 109 110 #define mmTPC5_QM_PQ_CI_3 0xF480BC 111 112 #define mmTPC5_QM_PQ_CFG0_0 0xF480C0 113 114 #define mmTPC5_QM_PQ_CFG0_1 0xF480C4 115 116 #define mmTPC5_QM_PQ_CFG0_2 0xF480C8 117 118 #define mmTPC5_QM_PQ_CFG0_3 0xF480CC 119 120 #define mmTPC5_QM_PQ_CFG1_0 0xF480D0 121 122 #define mmTPC5_QM_PQ_CFG1_1 0xF480D4 123 124 #define mmTPC5_QM_PQ_CFG1_2 0xF480D8 125 126 #define mmTPC5_QM_PQ_CFG1_3 0xF480DC 127 128 #define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0 129 130 #define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4 131 132 #define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8 133 134 #define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC 135 136 #define mmTPC5_QM_PQ_STS0_0 0xF480F0 137 138 #define mmTPC5_QM_PQ_STS0_1 0xF480F4 139 140 #define mmTPC5_QM_PQ_STS0_2 0xF480F8 141 142 #define mmTPC5_QM_PQ_STS0_3 0xF480FC 143 144 #define mmTPC5_QM_PQ_STS1_0 0xF48100 145 146 #define mmTPC5_QM_PQ_STS1_1 0xF48104 147 148 #define mmTPC5_QM_PQ_STS1_2 0xF48108 149 150 #define mmTPC5_QM_PQ_STS1_3 0xF4810C 151 152 #define mmTPC5_QM_CQ_CFG0_0 0xF48110 153 154 #define mmTPC5_QM_CQ_CFG0_1 0xF48114 155 156 #define mmTPC5_QM_CQ_CFG0_2 0xF48118 157 158 #define mmTPC5_QM_CQ_CFG0_3 0xF4811C 159 160 #define mmTPC5_QM_CQ_CFG0_4 0xF48120 161 162 #define mmTPC5_QM_CQ_CFG1_0 0xF48124 163 164 #define mmTPC5_QM_CQ_CFG1_1 0xF48128 165 166 #define mmTPC5_QM_CQ_CFG1_2 0xF4812C 167 168 #define mmTPC5_QM_CQ_CFG1_3 0xF48130 169 170 #define mmTPC5_QM_CQ_CFG1_4 0xF48134 171 172 #define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138 173 174 #define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C 175 176 #define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140 177 178 #define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144 179 180 #define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148 181 182 #define mmTPC5_QM_CQ_STS0_0 0xF4814C 183 184 #define mmTPC5_QM_CQ_STS0_1 0xF48150 185 186 #define mmTPC5_QM_CQ_STS0_2 0xF48154 187 188 #define mmTPC5_QM_CQ_STS0_3 0xF48158 189 190 #define mmTPC5_QM_CQ_STS0_4 0xF4815C 191 192 #define mmTPC5_QM_CQ_STS1_0 0xF48160 193 194 #define mmTPC5_QM_CQ_STS1_1 0xF48164 195 196 #define mmTPC5_QM_CQ_STS1_2 0xF48168 197 198 #define mmTPC5_QM_CQ_STS1_3 0xF4816C 199 200 #define mmTPC5_QM_CQ_STS1_4 0xF48170 201 202 #define mmTPC5_QM_CQ_PTR_LO_0 0xF48174 203 204 #define mmTPC5_QM_CQ_PTR_HI_0 0xF48178 205 206 #define mmTPC5_QM_CQ_TSIZE_0 0xF4817C 207 208 #define mmTPC5_QM_CQ_CTL_0 0xF48180 209 210 #define mmTPC5_QM_CQ_PTR_LO_1 0xF48184 211 212 #define mmTPC5_QM_CQ_PTR_HI_1 0xF48188 213 214 #define mmTPC5_QM_CQ_TSIZE_1 0xF4818C 215 216 #define mmTPC5_QM_CQ_CTL_1 0xF48190 217 218 #define mmTPC5_QM_CQ_PTR_LO_2 0xF48194 219 220 #define mmTPC5_QM_CQ_PTR_HI_2 0xF48198 221 222 #define mmTPC5_QM_CQ_TSIZE_2 0xF4819C 223 224 #define mmTPC5_QM_CQ_CTL_2 0xF481A0 225 226 #define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4 227 228 #define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8 229 230 #define mmTPC5_QM_CQ_TSIZE_3 0xF481AC 231 232 #define mmTPC5_QM_CQ_CTL_3 0xF481B0 233 234 #define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4 235 236 #define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8 237 238 #define mmTPC5_QM_CQ_TSIZE_4 0xF481BC 239 240 #define mmTPC5_QM_CQ_CTL_4 0xF481C0 241 242 #define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4 243 244 #define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8 245 246 #define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC 247 248 #define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0 249 250 #define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4 251 252 #define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8 253 254 #define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC 255 256 #define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0 257 258 #define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4 259 260 #define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8 261 262 #define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC 263 264 #define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0 265 266 #define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4 267 268 #define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8 269 270 #define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC 271 272 #define mmTPC5_QM_CQ_CTL_STS_0 0xF48200 273 274 #define mmTPC5_QM_CQ_CTL_STS_1 0xF48204 275 276 #define mmTPC5_QM_CQ_CTL_STS_2 0xF48208 277 278 #define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C 279 280 #define mmTPC5_QM_CQ_CTL_STS_4 0xF48210 281 282 #define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214 283 284 #define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218 285 286 #define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C 287 288 #define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220 289 290 #define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224 291 292 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228 293 294 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C 295 296 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230 297 298 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234 299 300 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238 301 302 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C 303 304 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240 305 306 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244 307 308 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248 309 310 #define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C 311 312 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250 313 314 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254 315 316 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258 317 318 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C 319 320 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260 321 322 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264 323 324 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268 325 326 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C 327 328 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270 329 330 #define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274 331 332 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278 333 334 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C 335 336 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280 337 338 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284 339 340 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288 341 342 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C 343 344 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290 345 346 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294 347 348 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298 349 350 #define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C 351 352 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0 353 354 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4 355 356 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8 357 358 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC 359 360 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0 361 362 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4 363 364 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8 365 366 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC 367 368 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0 369 370 #define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4 371 372 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8 373 374 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC 375 376 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0 377 378 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4 379 380 #define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8 381 382 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0 383 384 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4 385 386 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8 387 388 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC 389 390 #define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0 391 392 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4 393 394 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8 395 396 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC 397 398 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300 399 400 #define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304 401 402 #define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308 403 404 #define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C 405 406 #define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310 407 408 #define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314 409 410 #define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318 411 412 #define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C 413 414 #define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320 415 416 #define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324 417 418 #define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328 419 420 #define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C 421 422 #define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330 423 424 #define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334 425 426 #define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338 427 428 #define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C 429 430 #define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340 431 432 #define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344 433 434 #define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348 435 436 #define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C 437 438 #define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350 439 440 #define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354 441 442 #define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358 443 444 #define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C 445 446 #define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360 447 448 #define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364 449 450 #define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368 451 452 #define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C 453 454 #define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370 455 456 #define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374 457 458 #define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378 459 460 #define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C 461 462 #define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380 463 464 #define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384 465 466 #define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388 467 468 #define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C 469 470 #define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390 471 472 #define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394 473 474 #define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398 475 476 #define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C 477 478 #define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0 479 480 #define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4 481 482 #define mmTPC5_QM_CP_STS_0 0xF483A8 483 484 #define mmTPC5_QM_CP_STS_1 0xF483AC 485 486 #define mmTPC5_QM_CP_STS_2 0xF483B0 487 488 #define mmTPC5_QM_CP_STS_3 0xF483B4 489 490 #define mmTPC5_QM_CP_STS_4 0xF483B8 491 492 #define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC 493 494 #define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0 495 496 #define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4 497 498 #define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8 499 500 #define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC 501 502 #define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0 503 504 #define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4 505 506 #define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8 507 508 #define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC 509 510 #define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0 511 512 #define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4 513 514 #define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8 515 516 #define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC 517 518 #define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400 519 520 #define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404 521 522 #define mmTPC5_QM_CP_DBG_0_0 0xF48408 523 524 #define mmTPC5_QM_CP_DBG_0_1 0xF4840C 525 526 #define mmTPC5_QM_CP_DBG_0_2 0xF48410 527 528 #define mmTPC5_QM_CP_DBG_0_3 0xF48414 529 530 #define mmTPC5_QM_CP_DBG_0_4 0xF48418 531 532 #define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C 533 534 #define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420 535 536 #define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424 537 538 #define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428 539 540 #define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C 541 542 #define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430 543 544 #define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434 545 546 #define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438 547 548 #define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C 549 550 #define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440 551 552 #define mmTPC5_QM_ARB_CFG_0 0xF48A00 553 554 #define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04 555 556 #define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08 557 558 #define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C 559 560 #define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10 561 562 #define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14 563 564 #define mmTPC5_QM_ARB_CFG_1 0xF48A18 565 566 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20 567 568 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24 569 570 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28 571 572 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C 573 574 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30 575 576 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34 577 578 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38 579 580 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C 581 582 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40 583 584 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44 585 586 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48 587 588 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C 589 590 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50 591 592 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54 593 594 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58 595 596 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C 597 598 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60 599 600 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64 601 602 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68 603 604 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C 605 606 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70 607 608 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74 609 610 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78 611 612 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C 613 614 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80 615 616 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84 617 618 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88 619 620 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C 621 622 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90 623 624 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94 625 626 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98 627 628 #define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C 629 630 #define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0 631 632 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4 633 634 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8 635 636 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC 637 638 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0 639 640 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4 641 642 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8 643 644 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC 645 646 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0 647 648 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4 649 650 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8 651 652 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC 653 654 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0 655 656 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4 657 658 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8 659 660 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC 661 662 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0 663 664 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4 665 666 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8 667 668 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC 669 670 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0 671 672 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4 673 674 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8 675 676 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC 677 678 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00 679 680 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04 681 682 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08 683 684 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C 685 686 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10 687 688 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14 689 690 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18 691 692 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C 693 694 #define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20 695 696 #define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28 697 698 #define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C 699 700 #define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34 701 702 #define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38 703 704 #define mmTPC5_QM_ARB_SLV_ID 0xF48B3C 705 706 #define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44 707 708 #define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48 709 710 #define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C 711 712 #define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50 713 714 #define mmTPC5_QM_ARB_BASE_LO 0xF48B54 715 716 #define mmTPC5_QM_ARB_BASE_HI 0xF48B58 717 718 #define mmTPC5_QM_ARB_STATE_STS 0xF48B80 719 720 #define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84 721 722 #define mmTPC5_QM_ARB_MSG_STS 0xF48B88 723 724 #define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C 725 726 #define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C 727 728 #define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0 729 730 #define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8 731 732 #define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0 733 734 #define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4 735 736 #define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8 737 738 #define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC 739 740 #define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0 741 742 #define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4 743 744 #define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8 745 746 #define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC 747 748 #define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0 749 750 #define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4 751 752 #define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8 753 754 #define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC 755 756 #define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0 757 758 #define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4 759 760 #define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8 761 762 #define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC 763 764 #define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0 765 766 #define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4 767 768 #define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8 769 770 #define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC 771 772 #define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00 773 774 #define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04 775 776 #define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08 777 778 #define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C 779 780 #define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10 781 782 #define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14 783 784 #define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18 785 786 #define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C 787 788 #define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20 789 790 #define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24 791 792 #define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28 793 794 #define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C 795 796 #define mmTPC5_QM_CGM_CFG 0xF48C70 797 798 #define mmTPC5_QM_CGM_STS 0xF48C74 799 800 #define mmTPC5_QM_CGM_CFG1 0xF48C78 801 802 #define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80 803 804 #define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84 805 806 #define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90 807 808 #define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94 809 810 #define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98 811 812 #define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C 813 814 #define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0 815 816 #define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4 817 818 #define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0 819 820 #define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4 821 822 #define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8 823 824 #define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC 825 826 #define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0 827 828 #define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4 829 830 #define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8 831 832 #define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00 833 834 #endif /* ASIC_REG_TPC5_QM_REGS_H_ */ 835