1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_TPC0_CFG_MASKS_H_
14 #define ASIC_REG_TPC0_CFG_MASKS_H_
15 
16 /*
17  *****************************************
18  *   TPC0_CFG (Prototype: TPC)
19  *****************************************
20  */
21 
22 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT               0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
25 
26 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT              0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
29 
30 /* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT               0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK                0xFFFFFFFF
33 
34 /* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
37 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
39 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT        16
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
41 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT         19
42 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK          0x80000
43 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
44 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
45 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT          21
46 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK           0x600000
47 
48 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
49 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT                  0
50 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
51 
52 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
53 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT                0
54 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
55 
56 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
57 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT                  0
58 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
59 
60 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
61 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT                0
62 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
63 
64 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
65 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT                  0
66 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
67 
68 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
69 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT                0
70 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
71 
72 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
73 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT                  0
74 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
75 
76 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
77 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT                0
78 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
79 
80 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
81 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT                  0
82 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
83 
84 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
85 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT                0
86 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
87 
88 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
89 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT               0
90 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
91 
92 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
93 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT              0
94 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
95 
96 /* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
97 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT               0
98 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK                0xFFFFFFFF
99 
100 /* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
101 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
102 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
103 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
104 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
105 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT        16
106 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
107 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT         19
108 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK          0x80000
109 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
110 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
111 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT          21
112 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK           0x600000
113 
114 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
115 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT                  0
116 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
117 
118 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
119 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT                0
120 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
121 
122 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
123 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT                  0
124 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
125 
126 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
127 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT                0
128 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
129 
130 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
131 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT                  0
132 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
133 
134 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
135 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT                0
136 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
137 
138 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
139 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT                  0
140 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
141 
142 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
143 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT                0
144 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
145 
146 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
147 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT                  0
148 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
149 
150 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
151 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT                0
152 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
153 
154 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
155 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT               0
156 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
157 
158 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
159 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT              0
160 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
161 
162 /* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
163 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT               0
164 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK                0xFFFFFFFF
165 
166 /* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
167 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
168 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
169 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
170 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
171 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT        16
172 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
173 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT         19
174 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK          0x80000
175 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
176 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
177 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT          21
178 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK           0x600000
179 
180 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
181 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT                  0
182 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
183 
184 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
185 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT                0
186 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
187 
188 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
189 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT                  0
190 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
191 
192 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
193 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT                0
194 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
195 
196 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
197 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT                  0
198 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
199 
200 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
201 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT                0
202 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
203 
204 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
205 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT                  0
206 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
207 
208 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
209 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT                0
210 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
211 
212 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
213 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT                  0
214 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
215 
216 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
217 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT                0
218 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
219 
220 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
221 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT               0
222 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
223 
224 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
225 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT              0
226 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
227 
228 /* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
229 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT               0
230 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK                0xFFFFFFFF
231 
232 /* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
233 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
234 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
235 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
236 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
237 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT        16
238 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
239 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT         19
240 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK          0x80000
241 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
242 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
243 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT          21
244 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK           0x600000
245 
246 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
247 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT                  0
248 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
249 
250 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
251 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT                0
252 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
253 
254 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
255 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT                  0
256 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
257 
258 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
259 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT                0
260 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
261 
262 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
263 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT                  0
264 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
265 
266 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
267 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT                0
268 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
269 
270 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
271 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT                  0
272 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
273 
274 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
275 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT                0
276 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
277 
278 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
279 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT                  0
280 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
281 
282 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
283 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT                0
284 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
285 
286 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
287 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT               0
288 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
289 
290 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
291 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT              0
292 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
293 
294 /* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
295 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT               0
296 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK                0xFFFFFFFF
297 
298 /* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
299 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
300 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
301 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
302 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
303 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT        16
304 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
305 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT         19
306 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK          0x80000
307 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
308 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
309 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT          21
310 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK           0x600000
311 
312 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
313 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT                  0
314 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
315 
316 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
317 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT                0
318 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
319 
320 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
321 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT                  0
322 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
323 
324 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
325 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT                0
326 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
327 
328 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
329 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT                  0
330 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
331 
332 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
333 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT                0
334 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
335 
336 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
337 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT                  0
338 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
339 
340 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
341 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT                0
342 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
343 
344 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
345 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT                  0
346 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
347 
348 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
349 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT                0
350 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
351 
352 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
353 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT               0
354 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
355 
356 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
357 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT              0
358 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
359 
360 /* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
361 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT               0
362 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK                0xFFFFFFFF
363 
364 /* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
365 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
366 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
367 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
368 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
369 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT        16
370 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
371 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT         19
372 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK          0x80000
373 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
374 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
375 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT          21
376 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK           0x600000
377 
378 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
379 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT                  0
380 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
381 
382 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
383 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT                0
384 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
385 
386 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
387 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT                  0
388 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
389 
390 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
391 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT                0
392 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
393 
394 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
395 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT                  0
396 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
397 
398 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
399 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT                0
400 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
401 
402 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
403 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT                  0
404 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
405 
406 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
407 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT                0
408 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
409 
410 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
411 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT                  0
412 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
413 
414 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
415 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT                0
416 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
417 
418 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
419 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT               0
420 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
421 
422 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
423 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT              0
424 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
425 
426 /* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
427 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT               0
428 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK                0xFFFFFFFF
429 
430 /* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
431 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
432 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
433 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
434 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
435 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT        16
436 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
437 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT         19
438 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK          0x80000
439 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
440 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
441 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT          21
442 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK           0x600000
443 
444 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
445 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT                  0
446 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
447 
448 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
449 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT                0
450 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
451 
452 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
453 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT                  0
454 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
455 
456 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
457 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT                0
458 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
459 
460 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
461 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT                  0
462 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
463 
464 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
465 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT                0
466 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
467 
468 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
469 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT                  0
470 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
471 
472 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
473 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT                0
474 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
475 
476 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
477 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT                  0
478 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
479 
480 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
481 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT                0
482 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
483 
484 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
485 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT               0
486 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
487 
488 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
489 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT              0
490 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
491 
492 /* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
493 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT               0
494 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK                0xFFFFFFFF
495 
496 /* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
497 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
498 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
499 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
500 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
501 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT        16
502 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
503 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT         19
504 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK          0x80000
505 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
506 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
507 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT          21
508 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK           0x600000
509 
510 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
511 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT                  0
512 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
513 
514 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
515 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT                0
516 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
517 
518 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
519 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT                  0
520 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
521 
522 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
523 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT                0
524 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
525 
526 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
527 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT                  0
528 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
529 
530 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
531 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT                0
532 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
533 
534 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
535 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT                  0
536 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
537 
538 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
539 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT                0
540 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
541 
542 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
543 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT                  0
544 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
545 
546 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
547 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT                0
548 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
549 
550 /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */
551 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT               0
552 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
553 
554 /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */
555 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT              0
556 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
557 
558 /* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */
559 #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT               0
560 #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK                0xFFFFFFFF
561 
562 /* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */
563 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
564 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
565 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
566 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
567 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT        16
568 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
569 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT         19
570 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK          0x80000
571 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
572 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
573 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT          21
574 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK           0x600000
575 
576 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */
577 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT                  0
578 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
579 
580 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */
581 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT                0
582 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
583 
584 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */
585 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT                  0
586 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
587 
588 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */
589 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT                0
590 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
591 
592 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */
593 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT                  0
594 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
595 
596 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */
597 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT                0
598 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
599 
600 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */
601 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT                  0
602 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
603 
604 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */
605 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT                0
606 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
607 
608 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */
609 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT                  0
610 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
611 
612 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */
613 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT                0
614 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
615 
616 /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */
617 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT               0
618 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
619 
620 /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */
621 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT              0
622 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
623 
624 /* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */
625 #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT               0
626 #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK                0xFFFFFFFF
627 
628 /* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */
629 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
630 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
631 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
632 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
633 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT        16
634 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
635 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT         19
636 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK          0x80000
637 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
638 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
639 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT          21
640 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK           0x600000
641 
642 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */
643 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT                  0
644 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
645 
646 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */
647 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT                0
648 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
649 
650 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */
651 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT                  0
652 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
653 
654 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */
655 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT                0
656 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
657 
658 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */
659 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT                  0
660 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
661 
662 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */
663 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT                0
664 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
665 
666 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */
667 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT                  0
668 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
669 
670 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */
671 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT                0
672 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
673 
674 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */
675 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT                  0
676 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
677 
678 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */
679 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT                0
680 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
681 
682 /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */
683 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT              0
684 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
685 
686 /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */
687 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT             0
688 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
689 
690 /* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */
691 #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT              0
692 #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK               0xFFFFFFFF
693 
694 /* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */
695 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
696 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
697 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
698 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
699 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT       16
700 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
701 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT        19
702 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK         0x80000
703 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
704 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
705 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT         21
706 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK          0x600000
707 
708 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */
709 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT                 0
710 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
711 
712 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */
713 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT               0
714 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
715 
716 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */
717 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT                 0
718 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
719 
720 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */
721 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT               0
722 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
723 
724 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */
725 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT                 0
726 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
727 
728 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */
729 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT               0
730 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
731 
732 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */
733 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT                 0
734 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
735 
736 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */
737 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT               0
738 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
739 
740 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */
741 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT                 0
742 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
743 
744 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */
745 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT               0
746 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
747 
748 /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */
749 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT              0
750 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
751 
752 /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */
753 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT             0
754 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
755 
756 /* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */
757 #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT              0
758 #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK               0xFFFFFFFF
759 
760 /* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */
761 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
762 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
763 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
764 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
765 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT       16
766 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
767 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT        19
768 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK         0x80000
769 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
770 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
771 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT         21
772 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK          0x600000
773 
774 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */
775 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT                 0
776 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
777 
778 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */
779 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT               0
780 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
781 
782 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */
783 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT                 0
784 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
785 
786 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */
787 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT               0
788 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
789 
790 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */
791 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT                 0
792 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
793 
794 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */
795 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT               0
796 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
797 
798 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */
799 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT                 0
800 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
801 
802 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */
803 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT               0
804 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
805 
806 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */
807 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT                 0
808 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
809 
810 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */
811 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT               0
812 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
813 
814 /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */
815 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT              0
816 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
817 
818 /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */
819 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT             0
820 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
821 
822 /* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */
823 #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT              0
824 #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK               0xFFFFFFFF
825 
826 /* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */
827 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
828 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
829 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
830 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
831 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT       16
832 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
833 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT        19
834 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK         0x80000
835 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
836 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
837 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT         21
838 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK          0x600000
839 
840 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */
841 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT                 0
842 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
843 
844 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */
845 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT               0
846 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
847 
848 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */
849 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT                 0
850 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
851 
852 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */
853 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT               0
854 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
855 
856 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */
857 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT                 0
858 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
859 
860 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */
861 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT               0
862 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
863 
864 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */
865 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT                 0
866 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
867 
868 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */
869 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT               0
870 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
871 
872 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */
873 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT                 0
874 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
875 
876 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */
877 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT               0
878 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
879 
880 /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */
881 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT              0
882 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
883 
884 /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */
885 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT             0
886 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
887 
888 /* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */
889 #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT              0
890 #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK               0xFFFFFFFF
891 
892 /* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */
893 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
894 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
895 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
896 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
897 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT       16
898 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
899 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT        19
900 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK         0x80000
901 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
902 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
903 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT         21
904 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK          0x600000
905 
906 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */
907 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT                 0
908 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
909 
910 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */
911 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT               0
912 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
913 
914 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */
915 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT                 0
916 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
917 
918 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */
919 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT               0
920 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
921 
922 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */
923 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT                 0
924 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
925 
926 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */
927 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT               0
928 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
929 
930 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */
931 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT                 0
932 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
933 
934 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */
935 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT               0
936 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
937 
938 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */
939 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT                 0
940 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
941 
942 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */
943 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT               0
944 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
945 
946 /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */
947 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT              0
948 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
949 
950 /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */
951 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT             0
952 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
953 
954 /* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */
955 #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT              0
956 #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK               0xFFFFFFFF
957 
958 /* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */
959 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
960 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
961 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
962 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
963 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT       16
964 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
965 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT        19
966 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK         0x80000
967 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
968 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
969 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT         21
970 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK          0x600000
971 
972 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */
973 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT                 0
974 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
975 
976 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */
977 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT               0
978 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
979 
980 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */
981 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT                 0
982 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
983 
984 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */
985 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT               0
986 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
987 
988 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */
989 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT                 0
990 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
991 
992 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */
993 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT               0
994 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
995 
996 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */
997 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT                 0
998 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
999 
1000 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */
1001 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT               0
1002 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
1003 
1004 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */
1005 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT                 0
1006 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
1007 
1008 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */
1009 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT               0
1010 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
1011 
1012 /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */
1013 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT              0
1014 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
1015 
1016 /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */
1017 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT             0
1018 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
1019 
1020 /* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */
1021 #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT              0
1022 #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK               0xFFFFFFFF
1023 
1024 /* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */
1025 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
1026 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
1027 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
1028 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
1029 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT       16
1030 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
1031 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT        19
1032 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK         0x80000
1033 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
1034 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
1035 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT         21
1036 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK          0x600000
1037 
1038 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */
1039 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT                 0
1040 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
1041 
1042 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */
1043 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT               0
1044 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
1045 
1046 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */
1047 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT                 0
1048 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
1049 
1050 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */
1051 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT               0
1052 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
1053 
1054 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */
1055 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT                 0
1056 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
1057 
1058 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */
1059 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT               0
1060 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
1061 
1062 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */
1063 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT                 0
1064 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
1065 
1066 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */
1067 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT               0
1068 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
1069 
1070 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */
1071 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT                 0
1072 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
1073 
1074 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */
1075 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT               0
1076 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
1077 
1078 /* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
1079 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT     0
1080 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK      0xFFFF
1081 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT                16
1082 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK                 0x1FFF0000
1083 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT       29
1084 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK        0xE0000000
1085 
1086 /* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */
1087 #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT                     0
1088 #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK                      0xFFFFFFFF
1089 
1090 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
1091 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT              0
1092 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK               0xFFFFFFFF
1093 
1094 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
1095 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT             0
1096 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK              0xFFFFFFFF
1097 
1098 /* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
1099 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT                       0
1100 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK                        0xFFFFFFFF
1101 
1102 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
1103 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT                       0
1104 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK                        0xFFFFFFFF
1105 
1106 /* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
1107 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT                       0
1108 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK                        0xFFFFFFFF
1109 
1110 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
1111 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT                       0
1112 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK                        0xFFFFFFFF
1113 
1114 /* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
1115 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT                       0
1116 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK                        0xFFFFFFFF
1117 
1118 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
1119 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT                       0
1120 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK                        0xFFFFFFFF
1121 
1122 /* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
1123 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT                       0
1124 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK                        0xFFFFFFFF
1125 
1126 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
1127 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT                       0
1128 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK                        0xFFFFFFFF
1129 
1130 /* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
1131 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT                       0
1132 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK                        0xFFFFFFFF
1133 
1134 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
1135 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT                       0
1136 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK                        0xFFFFFFFF
1137 
1138 /* TPC0_CFG_KERNEL_KERNEL_CONFIG */
1139 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT                0
1140 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK                 0x1
1141 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT             1
1142 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK              0x2
1143 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT           2
1144 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK            0xFC
1145 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT  8
1146 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK   0xFF00
1147 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT  16
1148 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK   0xFF0000
1149 
1150 /* TPC0_CFG_KERNEL_KERNEL_ID */
1151 #define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT                            0
1152 #define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK                             0xFFFF
1153 
1154 /* TPC0_CFG_KERNEL_SRF */
1155 #define TPC0_CFG_KERNEL_SRF_V_SHIFT                                  0
1156 #define TPC0_CFG_KERNEL_SRF_V_MASK                                   0xFFFFFFFF
1157 
1158 /* TPC0_CFG_ROUND_CSR */
1159 #define TPC0_CFG_ROUND_CSR_MODE_SHIFT                                0
1160 #define TPC0_CFG_ROUND_CSR_MODE_MASK                                 0x7
1161 
1162 /* TPC0_CFG_PROT */
1163 #define TPC0_CFG_PROT_AWPROT_SHIFT                                   0
1164 #define TPC0_CFG_PROT_AWPROT_MASK                                    0x7
1165 #define TPC0_CFG_PROT_ARPROT_SHIFT                                   3
1166 #define TPC0_CFG_PROT_ARPROT_MASK                                    0x38
1167 
1168 /* TPC0_CFG_SEMAPHORE */
1169 #define TPC0_CFG_SEMAPHORE_V_SHIFT                                   0
1170 #define TPC0_CFG_SEMAPHORE_V_MASK                                    0xFFFFFFFF
1171 
1172 /* TPC0_CFG_VFLAGS */
1173 #define TPC0_CFG_VFLAGS_V_SHIFT                                      0
1174 #define TPC0_CFG_VFLAGS_V_MASK                                       0xF
1175 
1176 /* TPC0_CFG_SFLAGS */
1177 #define TPC0_CFG_SFLAGS_V_SHIFT                                      0
1178 #define TPC0_CFG_SFLAGS_V_MASK                                       0xF
1179 
1180 /* TPC0_CFG_LFSR_POLYNOM */
1181 #define TPC0_CFG_LFSR_POLYNOM_V_SHIFT                                0
1182 #define TPC0_CFG_LFSR_POLYNOM_V_MASK                                 0xFFFFFFFF
1183 
1184 /* TPC0_CFG_STATUS */
1185 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT                      1
1186 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK                       0x2
1187 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT                      2
1188 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK                       0x4
1189 #define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT                               3
1190 #define TPC0_CFG_STATUS_IQ_EMPTY_MASK                                0x8
1191 #define TPC0_CFG_STATUS_SB_EMPTY_SHIFT                               5
1192 #define TPC0_CFG_STATUS_SB_EMPTY_MASK                                0x20
1193 #define TPC0_CFG_STATUS_QM_IDLE_SHIFT                                6
1194 #define TPC0_CFG_STATUS_QM_IDLE_MASK                                 0x40
1195 #define TPC0_CFG_STATUS_QM_RDY_SHIFT                                 7
1196 #define TPC0_CFG_STATUS_QM_RDY_MASK                                  0x80
1197 
1198 /* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
1199 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT                       0
1200 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK                        0xFFFFFFFF
1201 
1202 /* TPC0_CFG_CFG_SUBTRACT_VALUE */
1203 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT                          0
1204 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK                           0xFFFFFFFF
1205 
1206 /* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
1207 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT                        0
1208 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK                         0xFFFFFFFF
1209 
1210 /* TPC0_CFG_TPC_CMD */
1211 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT                     0
1212 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK                      0x1
1213 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT                     1
1214 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK                      0x2
1215 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT                     2
1216 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK                      0x4
1217 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT                     3
1218 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK                      0x8
1219 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT                  4
1220 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK                   0x10
1221 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT                  5
1222 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK                   0x20
1223 #define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT                             6
1224 #define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK                              0x40
1225 
1226 /* TPC0_CFG_TPC_EXECUTE */
1227 #define TPC0_CFG_TPC_EXECUTE_V_SHIFT                                 0
1228 #define TPC0_CFG_TPC_EXECUTE_V_MASK                                  0x1
1229 
1230 /* TPC0_CFG_TPC_STALL */
1231 #define TPC0_CFG_TPC_STALL_V_SHIFT                                   0
1232 #define TPC0_CFG_TPC_STALL_V_MASK                                    0x1
1233 
1234 /* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
1235 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT                    0
1236 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK                     0xFFFFFFFF
1237 
1238 /* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
1239 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT                   0
1240 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK                    0xFFFFFFFF
1241 
1242 /* TPC0_CFG_RD_RATE_LIMIT */
1243 #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT                          0
1244 #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK                           0x1
1245 #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT                      1
1246 #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK                       0x1FE
1247 #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT                         9
1248 #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
1249 
1250 /* TPC0_CFG_WR_RATE_LIMIT */
1251 #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT                          0
1252 #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK                           0x1
1253 #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT                      1
1254 #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK                       0x1FE
1255 #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT                         9
1256 #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
1257 
1258 /* TPC0_CFG_MSS_CONFIG */
1259 #define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT                            0
1260 #define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK                             0xF
1261 #define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT                            4
1262 #define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK                             0xF0
1263 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT              8
1264 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK               0x300
1265 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT                   10
1266 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK                    0x400
1267 #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT                11
1268 #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK                 0x800
1269 
1270 /* TPC0_CFG_TPC_INTR_CAUSE */
1271 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT                          0
1272 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK                           0xFFFFF
1273 
1274 /* TPC0_CFG_TPC_INTR_MASK */
1275 #define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT                            0
1276 #define TPC0_CFG_TPC_INTR_MASK_MASK_MASK                             0xFFFFF
1277 
1278 /* TPC0_CFG_WQ_CREDITS */
1279 #define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT                               0
1280 #define TPC0_CFG_WQ_CREDITS_ST_G_MASK                                0xF
1281 #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT                        4
1282 #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK                         0x70
1283 
1284 /* TPC0_CFG_ARUSER_LO */
1285 #define TPC0_CFG_ARUSER_LO_V_SHIFT                                   0
1286 #define TPC0_CFG_ARUSER_LO_V_MASK                                    0x7FF
1287 
1288 /* TPC0_CFG_ARUSER_HI */
1289 #define TPC0_CFG_ARUSER_HI_V_SHIFT                                   11
1290 #define TPC0_CFG_ARUSER_HI_V_MASK                                    0x1800
1291 #define TPC0_CFG_ARUSER_HI_RSRV_SHIFT                                13
1292 #define TPC0_CFG_ARUSER_HI_RSRV_MASK                                 0xFFFFE000
1293 
1294 /* TPC0_CFG_AWUSER_LO */
1295 #define TPC0_CFG_AWUSER_LO_V_SHIFT                                   0
1296 #define TPC0_CFG_AWUSER_LO_V_MASK                                    0x7FF
1297 
1298 /* TPC0_CFG_AWUSER_HI */
1299 #define TPC0_CFG_AWUSER_HI_V_SHIFT                                   11
1300 #define TPC0_CFG_AWUSER_HI_V_MASK                                    0x1800
1301 #define TPC0_CFG_AWUSER_HI_RSRV_SHIFT                                13
1302 #define TPC0_CFG_AWUSER_HI_RSRV_MASK                                 0xFFFFE000
1303 
1304 /* TPC0_CFG_OPCODE_EXEC */
1305 #define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT                            0
1306 #define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK                             0x7F
1307 #define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT                            7
1308 #define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK                             0x80
1309 #define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT                            8
1310 #define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK                             0x7F00
1311 #define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT                            15
1312 #define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK                             0x8000
1313 #define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT                             16
1314 #define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK                              0x7F0000
1315 #define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT                             23
1316 #define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK                              0x800000
1317 #define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT                             24
1318 #define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK                              0x7F000000
1319 #define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT                             31
1320 #define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK                              0x80000000
1321 
1322 /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */
1323 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT                     0
1324 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
1325 
1326 /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */
1327 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT                     0
1328 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
1329 
1330 /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */
1331 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT                     0
1332 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
1333 
1334 /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */
1335 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT                     0
1336 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
1337 
1338 /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */
1339 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT                    0
1340 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
1341 
1342 /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */
1343 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT                    0
1344 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
1345 
1346 /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */
1347 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT                    0
1348 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
1349 
1350 /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */
1351 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT                    0
1352 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
1353 
1354 /* TPC0_CFG_TSB_CFG_MAX_SIZE */
1355 #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT                         0
1356 #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK                          0xFFFF
1357 #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT                           16
1358 #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK                            0xFFFF0000
1359 
1360 /* TPC0_CFG_TSB_CFG */
1361 #define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT                            0
1362 #define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK                             0x1
1363 #define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT                                1
1364 #define TPC0_CFG_TSB_CFG_MAX_OS_MASK                                 0x1FFFE
1365 
1366 /* TPC0_CFG_DBGMEM_ADD */
1367 #define TPC0_CFG_DBGMEM_ADD_V_SHIFT                                  0
1368 #define TPC0_CFG_DBGMEM_ADD_V_MASK                                   0xFFFFFFFF
1369 
1370 /* TPC0_CFG_DBGMEM_DATA_WR */
1371 #define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT                              0
1372 #define TPC0_CFG_DBGMEM_DATA_WR_V_MASK                               0xFFFFFFFF
1373 
1374 /* TPC0_CFG_DBGMEM_DATA_RD */
1375 #define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT                              0
1376 #define TPC0_CFG_DBGMEM_DATA_RD_V_MASK                               0xFFFFFFFF
1377 
1378 /* TPC0_CFG_DBGMEM_CTRL */
1379 #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT                            0
1380 #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK                             0x1
1381 
1382 /* TPC0_CFG_DBGMEM_RC */
1383 #define TPC0_CFG_DBGMEM_RC_VALID_SHIFT                               0
1384 #define TPC0_CFG_DBGMEM_RC_VALID_MASK                                0x1
1385 
1386 /* TPC0_CFG_TSB_INFLIGHT_CNTR */
1387 #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT                           0
1388 #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK                            0xFFFFFFFF
1389 
1390 /* TPC0_CFG_WQ_INFLIGHT_CNTR */
1391 #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT                          0
1392 #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK                           0xFFFF
1393 #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT                          16
1394 #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK                           0xF0000
1395 
1396 /* TPC0_CFG_WQ_LBW_TOTAL_CNTR */
1397 #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT                           0
1398 #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
1399 
1400 /* TPC0_CFG_WQ_HBW_TOTAL_CNTR */
1401 #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT                           0
1402 #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
1403 
1404 /* TPC0_CFG_IRQ_OCCOUPY_CNTR */
1405 #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT                            0
1406 #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK                             0xFFFFFFFF
1407 
1408 /* TPC0_CFG_FUNC_MBIST_CNTRL */
1409 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT                  0
1410 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK                   0x1
1411 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT                   1
1412 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK                    0x2
1413 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT                 2
1414 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK                  0x4
1415 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT                 16
1416 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK                  0x3FF0000
1417 
1418 /* TPC0_CFG_FUNC_MBIST_PAT */
1419 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT            0
1420 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK             0x3
1421 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT             2
1422 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK              0xC
1423 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT            4
1424 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK             0x30
1425 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT             6
1426 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK              0xC0
1427 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT            8
1428 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK             0x300
1429 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT             10
1430 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK              0xC00
1431 
1432 /* TPC0_CFG_FUNC_MBIST_MEM */
1433 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT                       0
1434 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK                        0x7FF
1435 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT                     12
1436 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK                      0x7000
1437 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT               16
1438 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK                0x7FF0000
1439 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT            28
1440 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK             0x70000000
1441 
1442 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
1443 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT                   0
1444 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1445 
1446 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
1447 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT                  0
1448 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1449 
1450 /* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
1451 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT                   0
1452 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1453 
1454 /* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
1455 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1456 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1457 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1458 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1459 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1460 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1461 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT             19
1462 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1463 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1464 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1465 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT              21
1466 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1467 
1468 /* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
1469 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT                      0
1470 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1471 
1472 /* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
1473 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT                    0
1474 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1475 
1476 /* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
1477 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT                      0
1478 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1479 
1480 /* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
1481 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT                    0
1482 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1483 
1484 /* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
1485 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT                      0
1486 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1487 
1488 /* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
1489 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT                    0
1490 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1491 
1492 /* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
1493 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT                      0
1494 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1495 
1496 /* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
1497 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT                    0
1498 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1499 
1500 /* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
1501 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT                      0
1502 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1503 
1504 /* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
1505 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT                    0
1506 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1507 
1508 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
1509 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT                   0
1510 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1511 
1512 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
1513 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT                  0
1514 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1515 
1516 /* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
1517 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT                   0
1518 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1519 
1520 /* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
1521 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1522 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1523 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1524 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1525 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1526 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1527 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT             19
1528 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1529 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1530 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1531 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT              21
1532 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1533 
1534 /* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
1535 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT                      0
1536 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1537 
1538 /* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
1539 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT                    0
1540 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1541 
1542 /* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
1543 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT                      0
1544 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1545 
1546 /* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
1547 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT                    0
1548 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1549 
1550 /* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
1551 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT                      0
1552 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1553 
1554 /* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
1555 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT                    0
1556 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1557 
1558 /* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
1559 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT                      0
1560 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1561 
1562 /* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
1563 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT                    0
1564 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1565 
1566 /* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
1567 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT                      0
1568 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1569 
1570 /* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
1571 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT                    0
1572 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1573 
1574 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
1575 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT                   0
1576 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1577 
1578 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
1579 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT                  0
1580 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1581 
1582 /* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
1583 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT                   0
1584 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1585 
1586 /* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
1587 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1588 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1589 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1590 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1591 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1592 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1593 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT             19
1594 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1595 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1596 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1597 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT              21
1598 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1599 
1600 /* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
1601 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT                      0
1602 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1603 
1604 /* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
1605 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT                    0
1606 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1607 
1608 /* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
1609 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT                      0
1610 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1611 
1612 /* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
1613 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT                    0
1614 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1615 
1616 /* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
1617 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT                      0
1618 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1619 
1620 /* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
1621 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT                    0
1622 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1623 
1624 /* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
1625 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT                      0
1626 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1627 
1628 /* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
1629 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT                    0
1630 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1631 
1632 /* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
1633 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT                      0
1634 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1635 
1636 /* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
1637 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT                    0
1638 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1639 
1640 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
1641 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT                   0
1642 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1643 
1644 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
1645 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT                  0
1646 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1647 
1648 /* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
1649 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT                   0
1650 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1651 
1652 /* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
1653 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1654 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1655 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1656 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1657 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1658 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1659 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT             19
1660 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1661 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1662 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1663 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT              21
1664 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1665 
1666 /* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
1667 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT                      0
1668 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1669 
1670 /* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
1671 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT                    0
1672 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1673 
1674 /* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
1675 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT                      0
1676 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1677 
1678 /* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
1679 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT                    0
1680 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1681 
1682 /* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
1683 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT                      0
1684 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1685 
1686 /* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
1687 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT                    0
1688 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1689 
1690 /* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
1691 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT                      0
1692 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1693 
1694 /* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
1695 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT                    0
1696 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1697 
1698 /* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
1699 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT                      0
1700 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1701 
1702 /* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
1703 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT                    0
1704 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1705 
1706 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
1707 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT                   0
1708 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1709 
1710 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
1711 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT                  0
1712 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1713 
1714 /* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
1715 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT                   0
1716 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1717 
1718 /* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
1719 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1720 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1721 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1722 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1723 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1724 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1725 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT             19
1726 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1727 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1728 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1729 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT              21
1730 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1731 
1732 /* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
1733 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT                      0
1734 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1735 
1736 /* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
1737 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT                    0
1738 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1739 
1740 /* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
1741 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT                      0
1742 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1743 
1744 /* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
1745 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT                    0
1746 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1747 
1748 /* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
1749 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT                      0
1750 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1751 
1752 /* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
1753 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT                    0
1754 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1755 
1756 /* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
1757 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT                      0
1758 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1759 
1760 /* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
1761 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT                    0
1762 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1763 
1764 /* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
1765 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT                      0
1766 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1767 
1768 /* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
1769 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT                    0
1770 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1771 
1772 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
1773 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT                   0
1774 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1775 
1776 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
1777 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT                  0
1778 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1779 
1780 /* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
1781 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT                   0
1782 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1783 
1784 /* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
1785 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1786 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1787 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1788 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1789 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1790 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1791 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT             19
1792 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1793 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1794 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1795 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT              21
1796 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1797 
1798 /* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
1799 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT                      0
1800 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1801 
1802 /* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
1803 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT                    0
1804 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1805 
1806 /* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
1807 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT                      0
1808 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1809 
1810 /* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
1811 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT                    0
1812 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1813 
1814 /* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
1815 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT                      0
1816 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1817 
1818 /* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
1819 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT                    0
1820 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1821 
1822 /* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
1823 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT                      0
1824 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1825 
1826 /* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
1827 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT                    0
1828 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1829 
1830 /* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
1831 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT                      0
1832 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1833 
1834 /* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
1835 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT                    0
1836 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1837 
1838 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
1839 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT                   0
1840 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1841 
1842 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
1843 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT                  0
1844 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1845 
1846 /* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
1847 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT                   0
1848 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1849 
1850 /* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
1851 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1852 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1853 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1854 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1855 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1856 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1857 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT             19
1858 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1859 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1860 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1861 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT              21
1862 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1863 
1864 /* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
1865 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT                      0
1866 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1867 
1868 /* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
1869 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT                    0
1870 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1871 
1872 /* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
1873 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT                      0
1874 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1875 
1876 /* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
1877 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT                    0
1878 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1879 
1880 /* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
1881 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT                      0
1882 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1883 
1884 /* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
1885 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT                    0
1886 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1887 
1888 /* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
1889 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT                      0
1890 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1891 
1892 /* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
1893 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT                    0
1894 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1895 
1896 /* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
1897 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT                      0
1898 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1899 
1900 /* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
1901 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT                    0
1902 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1903 
1904 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
1905 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT                   0
1906 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1907 
1908 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
1909 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT                  0
1910 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1911 
1912 /* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
1913 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT                   0
1914 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1915 
1916 /* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
1917 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1918 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1919 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1920 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1921 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1922 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1923 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT             19
1924 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1925 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1926 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1927 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT              21
1928 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1929 
1930 /* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
1931 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT                      0
1932 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1933 
1934 /* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
1935 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT                    0
1936 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
1937 
1938 /* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
1939 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT                      0
1940 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
1941 
1942 /* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
1943 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT                    0
1944 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
1945 
1946 /* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
1947 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT                      0
1948 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
1949 
1950 /* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
1951 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT                    0
1952 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
1953 
1954 /* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
1955 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT                      0
1956 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
1957 
1958 /* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
1959 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT                    0
1960 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
1961 
1962 /* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
1963 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT                      0
1964 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
1965 
1966 /* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
1967 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT                    0
1968 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
1969 
1970 /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */
1971 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT                   0
1972 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
1973 
1974 /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */
1975 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT                  0
1976 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
1977 
1978 /* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */
1979 #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT                   0
1980 #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK                    0xFFFFFFFF
1981 
1982 /* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */
1983 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
1984 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
1985 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
1986 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
1987 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT            16
1988 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
1989 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT             19
1990 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK              0x80000
1991 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
1992 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
1993 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT              21
1994 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK               0x600000
1995 
1996 /* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */
1997 #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT                      0
1998 #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
1999 
2000 /* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */
2001 #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT                    0
2002 #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
2003 
2004 /* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */
2005 #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT                      0
2006 #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
2007 
2008 /* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */
2009 #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT                    0
2010 #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
2011 
2012 /* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */
2013 #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT                      0
2014 #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
2015 
2016 /* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */
2017 #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT                    0
2018 #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
2019 
2020 /* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */
2021 #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT                      0
2022 #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
2023 
2024 /* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */
2025 #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT                    0
2026 #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
2027 
2028 /* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */
2029 #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT                      0
2030 #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
2031 
2032 /* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */
2033 #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT                    0
2034 #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
2035 
2036 /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */
2037 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT                   0
2038 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
2039 
2040 /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */
2041 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT                  0
2042 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
2043 
2044 /* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */
2045 #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT                   0
2046 #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK                    0xFFFFFFFF
2047 
2048 /* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */
2049 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
2050 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
2051 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
2052 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
2053 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT            16
2054 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
2055 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT             19
2056 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK              0x80000
2057 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
2058 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
2059 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT              21
2060 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK               0x600000
2061 
2062 /* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */
2063 #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT                      0
2064 #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
2065 
2066 /* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */
2067 #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT                    0
2068 #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
2069 
2070 /* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */
2071 #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT                      0
2072 #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
2073 
2074 /* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */
2075 #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT                    0
2076 #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
2077 
2078 /* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */
2079 #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT                      0
2080 #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
2081 
2082 /* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */
2083 #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT                    0
2084 #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
2085 
2086 /* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */
2087 #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT                      0
2088 #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
2089 
2090 /* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */
2091 #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT                    0
2092 #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
2093 
2094 /* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */
2095 #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT                      0
2096 #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
2097 
2098 /* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */
2099 #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT                    0
2100 #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
2101 
2102 /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */
2103 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT                  0
2104 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2105 
2106 /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */
2107 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT                 0
2108 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2109 
2110 /* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */
2111 #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT                  0
2112 #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2113 
2114 /* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */
2115 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2116 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2117 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2118 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2119 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2120 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2121 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT            19
2122 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2123 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2124 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2125 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT             21
2126 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2127 
2128 /* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */
2129 #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT                     0
2130 #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2131 
2132 /* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */
2133 #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT                   0
2134 #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2135 
2136 /* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */
2137 #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT                     0
2138 #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2139 
2140 /* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */
2141 #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT                   0
2142 #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2143 
2144 /* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */
2145 #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT                     0
2146 #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2147 
2148 /* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */
2149 #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT                   0
2150 #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2151 
2152 /* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */
2153 #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT                     0
2154 #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2155 
2156 /* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */
2157 #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT                   0
2158 #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2159 
2160 /* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */
2161 #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT                     0
2162 #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2163 
2164 /* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */
2165 #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT                   0
2166 #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2167 
2168 /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */
2169 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT                  0
2170 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2171 
2172 /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */
2173 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT                 0
2174 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2175 
2176 /* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */
2177 #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT                  0
2178 #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2179 
2180 /* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */
2181 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2182 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2183 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2184 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2185 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2186 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2187 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT            19
2188 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2189 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2190 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2191 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT             21
2192 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2193 
2194 /* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */
2195 #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT                     0
2196 #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2197 
2198 /* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */
2199 #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT                   0
2200 #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2201 
2202 /* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */
2203 #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT                     0
2204 #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2205 
2206 /* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */
2207 #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT                   0
2208 #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2209 
2210 /* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */
2211 #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT                     0
2212 #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2213 
2214 /* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */
2215 #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT                   0
2216 #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2217 
2218 /* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */
2219 #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT                     0
2220 #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2221 
2222 /* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */
2223 #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT                   0
2224 #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2225 
2226 /* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */
2227 #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT                     0
2228 #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2229 
2230 /* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */
2231 #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT                   0
2232 #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2233 
2234 /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */
2235 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT                  0
2236 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2237 
2238 /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */
2239 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT                 0
2240 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2241 
2242 /* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */
2243 #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT                  0
2244 #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2245 
2246 /* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */
2247 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2248 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2249 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2250 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2251 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2252 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2253 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT            19
2254 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2255 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2256 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2257 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT             21
2258 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2259 
2260 /* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */
2261 #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT                     0
2262 #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2263 
2264 /* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */
2265 #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT                   0
2266 #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2267 
2268 /* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */
2269 #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT                     0
2270 #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2271 
2272 /* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */
2273 #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT                   0
2274 #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2275 
2276 /* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */
2277 #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT                     0
2278 #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2279 
2280 /* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */
2281 #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT                   0
2282 #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2283 
2284 /* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */
2285 #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT                     0
2286 #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2287 
2288 /* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */
2289 #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT                   0
2290 #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2291 
2292 /* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */
2293 #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT                     0
2294 #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2295 
2296 /* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */
2297 #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT                   0
2298 #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2299 
2300 /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */
2301 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT                  0
2302 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2303 
2304 /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */
2305 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT                 0
2306 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2307 
2308 /* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */
2309 #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT                  0
2310 #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2311 
2312 /* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */
2313 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2314 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2315 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2316 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2317 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2318 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2319 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT            19
2320 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2321 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2322 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2323 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT             21
2324 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2325 
2326 /* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */
2327 #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT                     0
2328 #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2329 
2330 /* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */
2331 #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT                   0
2332 #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2333 
2334 /* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */
2335 #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT                     0
2336 #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2337 
2338 /* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */
2339 #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT                   0
2340 #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2341 
2342 /* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */
2343 #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT                     0
2344 #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2345 
2346 /* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */
2347 #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT                   0
2348 #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2349 
2350 /* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */
2351 #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT                     0
2352 #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2353 
2354 /* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */
2355 #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT                   0
2356 #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2357 
2358 /* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */
2359 #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT                     0
2360 #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2361 
2362 /* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */
2363 #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT                   0
2364 #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2365 
2366 /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */
2367 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT                  0
2368 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2369 
2370 /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */
2371 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT                 0
2372 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2373 
2374 /* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */
2375 #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT                  0
2376 #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2377 
2378 /* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */
2379 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2380 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2381 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2382 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2383 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2384 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2385 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT            19
2386 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2387 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2388 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2389 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT             21
2390 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2391 
2392 /* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */
2393 #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT                     0
2394 #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2395 
2396 /* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */
2397 #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT                   0
2398 #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2399 
2400 /* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */
2401 #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT                     0
2402 #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2403 
2404 /* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */
2405 #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT                   0
2406 #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2407 
2408 /* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */
2409 #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT                     0
2410 #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2411 
2412 /* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */
2413 #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT                   0
2414 #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2415 
2416 /* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */
2417 #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT                     0
2418 #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2419 
2420 /* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */
2421 #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT                   0
2422 #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2423 
2424 /* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */
2425 #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT                     0
2426 #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2427 
2428 /* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */
2429 #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT                   0
2430 #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2431 
2432 /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */
2433 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT                  0
2434 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
2435 
2436 /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */
2437 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT                 0
2438 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
2439 
2440 /* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */
2441 #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT                  0
2442 #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK                   0xFFFFFFFF
2443 
2444 /* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */
2445 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
2446 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
2447 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
2448 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
2449 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT           16
2450 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
2451 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT            19
2452 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK             0x80000
2453 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
2454 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
2455 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT             21
2456 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK              0x600000
2457 
2458 /* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */
2459 #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT                     0
2460 #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
2461 
2462 /* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */
2463 #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT                   0
2464 #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
2465 
2466 /* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */
2467 #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT                     0
2468 #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
2469 
2470 /* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */
2471 #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT                   0
2472 #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
2473 
2474 /* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */
2475 #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT                     0
2476 #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
2477 
2478 /* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */
2479 #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT                   0
2480 #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
2481 
2482 /* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */
2483 #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT                     0
2484 #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
2485 
2486 /* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */
2487 #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT                   0
2488 #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
2489 
2490 /* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */
2491 #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT                     0
2492 #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
2493 
2494 /* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */
2495 #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT                   0
2496 #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
2497 
2498 /* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
2499 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT         0
2500 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK          0xFFFF
2501 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT                    16
2502 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK                     0x1FFF0000
2503 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT           29
2504 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK            0xE0000000
2505 
2506 /* TPC0_CFG_QM_SYNC_OBJECT_ADDR */
2507 #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT                         0
2508 #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK                          0xFFFFFFFF
2509 
2510 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
2511 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT                  0
2512 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK                   0xFFFFFFFF
2513 
2514 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
2515 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT                 0
2516 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK                  0xFFFFFFFF
2517 
2518 /* TPC0_CFG_QM_TID_BASE_DIM_0 */
2519 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT                           0
2520 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK                            0xFFFFFFFF
2521 
2522 /* TPC0_CFG_QM_TID_SIZE_DIM_0 */
2523 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT                           0
2524 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK                            0xFFFFFFFF
2525 
2526 /* TPC0_CFG_QM_TID_BASE_DIM_1 */
2527 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT                           0
2528 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK                            0xFFFFFFFF
2529 
2530 /* TPC0_CFG_QM_TID_SIZE_DIM_1 */
2531 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT                           0
2532 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK                            0xFFFFFFFF
2533 
2534 /* TPC0_CFG_QM_TID_BASE_DIM_2 */
2535 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT                           0
2536 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK                            0xFFFFFFFF
2537 
2538 /* TPC0_CFG_QM_TID_SIZE_DIM_2 */
2539 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT                           0
2540 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK                            0xFFFFFFFF
2541 
2542 /* TPC0_CFG_QM_TID_BASE_DIM_3 */
2543 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT                           0
2544 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK                            0xFFFFFFFF
2545 
2546 /* TPC0_CFG_QM_TID_SIZE_DIM_3 */
2547 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT                           0
2548 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK                            0xFFFFFFFF
2549 
2550 /* TPC0_CFG_QM_TID_BASE_DIM_4 */
2551 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT                           0
2552 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK                            0xFFFFFFFF
2553 
2554 /* TPC0_CFG_QM_TID_SIZE_DIM_4 */
2555 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT                           0
2556 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK                            0xFFFFFFFF
2557 
2558 /* TPC0_CFG_QM_KERNEL_CONFIG */
2559 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT                    0
2560 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK                     0x1
2561 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT                 1
2562 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK                  0x2
2563 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT               2
2564 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK                0xFC
2565 #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT      8
2566 #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK       0xFF00
2567 #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT      16
2568 #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK       0xFF0000
2569 
2570 /* TPC0_CFG_QM_KERNEL_ID */
2571 #define TPC0_CFG_QM_KERNEL_ID_V_SHIFT                                0
2572 #define TPC0_CFG_QM_KERNEL_ID_V_MASK                                 0xFFFF
2573 
2574 /* TPC0_CFG_QM_SRF */
2575 #define TPC0_CFG_QM_SRF_V_SHIFT                                      0
2576 #define TPC0_CFG_QM_SRF_V_MASK                                       0xFFFFFFFF
2577 
2578 #endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */
2579