1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PSOC_CPU_PLL_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PSOC_CPU_PLL (Prototype: PLL) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_NR 0xC70100 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_NF 0xC70104 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_OD 0xC70108 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_NB 0xC7010C 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CFG 0xC70110 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_LOSE_MASK 0xC70120 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_LOCK_INTR 0xC70128 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_LOCK_BYPASS 0xC7012C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DATA_CHNG 0xC70130 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RST 0xC70134 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_SLIP_WD_CNTR 0xC70150 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_0 0xC70200 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_1 0xC70204 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_2 0xC70208 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_3 0xC7020C 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0 0xC70220 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1 0xC70224 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2 0xC70228 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3 0xC7022C 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_SEL_0 0xC70280 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_SEL_1 0xC70284 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_SEL_2 0xC70288 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_SEL_3 0xC7028C 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_EN_0 0xC702A0 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_EN_1 0xC702A4 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_EN_2 0xC702A8 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_EN_3 0xC702AC 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0 0xC702C0 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1 0xC702C4 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2 0xC702C8 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3 0xC702CC 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CLK_GATER 0xC70300 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CLK_RLX_0 0xC70310 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CLK_RLX_1 0xC70314 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CLK_RLX_2 0xC70318 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_CLK_RLX_3 0xC7031C 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_REF_CNTR_PERIOD 0xC70400 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD 0xC70410 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD 0xC70420 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_PLL_NOT_STABLE 0xC70430 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_FREQ_CALC_EN 0xC70440 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RLX_BITMAP_CFG 0xC70500 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RLX_BITMAP_0 0xC70510 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RLX_BITMAP_1 0xC70514 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RLX_BITMAP_2 0xC70518 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_RLX_BITMAP_3 0xC7051C 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */ 115