1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_MMU_UP_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_MMU_UP_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * MMU_UP (Prototype: MMU) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmMMU_UP_MMU_ENABLE 0xC1100C 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmMMU_UP_FORCE_ORDERING 0xC11010 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmMMU_UP_FEATURE_ENABLE 0xC11014 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmMMU_UP_SCRAMBLER 0xC11024 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmMMU_UP_MEM_INIT_BUSY 0xC11028 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmMMU_UP_SPI_MASK 0xC1102C 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmMMU_UP_SPI_CAUSE 0xC11030 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmMMU_UP_SLICE_CREDIT 0xC11054 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmMMU_UP_PIPE_CREDIT 0xC11058 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmMMU_UP_RAZWI_READ_VLD 0xC11064 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmMMU_UP_RAZWI_READ_ID 0xC11068 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmMMU_UP_MMU_BYPASS 0xC1106C 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #endif /* ASIC_REG_MMU_UP_REGS_H_ */ 73