1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA5_CORE_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA5_CORE_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA5_CORE (Prototype: DMA_CORE) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmDMA5_CORE_CFG_0 0x5A0000 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmDMA5_CORE_CFG_1 0x5A0004 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmDMA5_CORE_LBW_MAX_OUTSTAND 0x5A0008 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_BASE_LO 0x5A0014 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_BASE_HI 0x5A0018 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_BASE_LO 0x5A001C 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_BASE_HI 0x5A0020 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_TSIZE_1 0x5A002C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_STRIDE_1 0x5A0030 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_TSIZE_2 0x5A0034 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_STRIDE_2 0x5A0038 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_TSIZE_3 0x5A003C 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_STRIDE_3 0x5A0040 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_TSIZE_4 0x5A0044 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_STRIDE_4 0x5A0048 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmDMA5_CORE_SRC_TSIZE_0 0x5A004C 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_TSIZE_1 0x5A0054 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_STRIDE_1 0x5A0058 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_TSIZE_2 0x5A005C 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_STRIDE_2 0x5A0060 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_TSIZE_3 0x5A0064 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_STRIDE_3 0x5A0068 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_TSIZE_4 0x5A006C 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_STRIDE_4 0x5A0070 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmDMA5_CORE_DST_TSIZE_0 0x5A0074 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmDMA5_CORE_COMMIT 0x5A0078 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_COMP_WDATA 0x5A007C 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_COMP_ADDR_LO 0x5A0080 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_COMP_ADDR_HI 0x5A0084 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_COMP_AWUSER_31_11 0x5A0088 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmDMA5_CORE_TE_NUMROWS 0x5A0094 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmDMA5_CORE_PROT 0x5A00B8 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmDMA5_CORE_SECURE_PROPS 0x5A00F0 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmDMA5_CORE_NON_SECURE_PROPS 0x5A00F4 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_MAX_OUTSTAND 0x5A0100 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_MAX_SIZE 0x5A0104 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_ARCACHE 0x5A0108 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_ARUSER_31_11 0x5A0110 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_INFLIGHTS 0x5A0114 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_MAX_OUTSTAND 0x5A0120 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_MAX_AWID 0x5A0124 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_AWCACHE 0x5A0128 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_AWUSER_31_11 0x5A0130 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_INFLIGHTS 0x5A0134 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_RATE_LIM_CFG_0 0x5A0150 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_RATE_LIM_CFG_1 0x5A0154 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_RATE_LIM_CFG_0 0x5A0158 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define mmDMA5_CORE_WR_RATE_LIM_CFG_1 0x5A015C 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay #define mmDMA5_CORE_ERR_CFG 0x5A0160 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay #define mmDMA5_CORE_ERR_CAUSE 0x5A0164 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define mmDMA5_CORE_ERRMSG_ADDR_LO 0x5A0170 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define mmDMA5_CORE_ERRMSG_ADDR_HI 0x5A0174 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay #define mmDMA5_CORE_ERRMSG_WDATA 0x5A0178 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define mmDMA5_CORE_STS0 0x5A0190 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay #define mmDMA5_CORE_STS1 0x5A0194 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_DBGMEM_ADD 0x5A0200 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_DBGMEM_DATA_WR 0x5A0204 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_DBGMEM_DATA_RD 0x5A0208 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_DBGMEM_CTRL 0x5A020C 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay #define mmDMA5_CORE_RD_DBGMEM_RC 0x5A0210 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT 0x5A0220 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT 0x5A0224 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT 0x5A0228 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_DESC_CNT 0x5A022C 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_STS 0x5A0230 151*e65e175bSOded Gabbay 152*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_RD_DESC_ID 0x5A0234 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define mmDMA5_CORE_DBG_WR_DESC_ID 0x5A0238 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA5_CORE_REGS_H_ */ 157