1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA2_CORE_REGS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA2_CORE_REGS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA2_CORE (Prototype: DMA_CORE) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay #define mmDMA2_CORE_CFG_0 0x540000 23*e65e175bSOded Gabbay 24*e65e175bSOded Gabbay #define mmDMA2_CORE_CFG_1 0x540004 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay #define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_BASE_LO 0x540014 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_BASE_HI 0x540018 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_BASE_LO 0x54001C 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_BASE_HI 0x540020 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_TSIZE_1 0x54002C 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_STRIDE_1 0x540030 39*e65e175bSOded Gabbay 40*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_TSIZE_2 0x540034 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_STRIDE_2 0x540038 43*e65e175bSOded Gabbay 44*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_TSIZE_3 0x54003C 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_STRIDE_3 0x540040 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_TSIZE_4 0x540044 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_STRIDE_4 0x540048 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay #define mmDMA2_CORE_SRC_TSIZE_0 0x54004C 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_TSIZE_1 0x540054 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_STRIDE_1 0x540058 57*e65e175bSOded Gabbay 58*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_TSIZE_2 0x54005C 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_STRIDE_2 0x540060 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_TSIZE_3 0x540064 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_STRIDE_3 0x540068 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_TSIZE_4 0x54006C 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_STRIDE_4 0x540070 69*e65e175bSOded Gabbay 70*e65e175bSOded Gabbay #define mmDMA2_CORE_DST_TSIZE_0 0x540074 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay #define mmDMA2_CORE_COMMIT 0x540078 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_COMP_WDATA 0x54007C 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay #define mmDMA2_CORE_TE_NUMROWS 0x540094 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay #define mmDMA2_CORE_PROT 0x5400B8 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay #define mmDMA2_CORE_SECURE_PROPS 0x5400F0 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_MAX_SIZE 0x540104 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_ARCACHE 0x540108 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_ARUSER_31_11 0x540110 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_INFLIGHTS 0x540114 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120 101*e65e175bSOded Gabbay 102*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_MAX_AWID 0x540124 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_AWCACHE 0x540128 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_AWUSER_31_11 0x540130 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_INFLIGHTS 0x540134 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay #define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay #define mmDMA2_CORE_ERR_CFG 0x540160 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay #define mmDMA2_CORE_ERR_CAUSE 0x540164 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay #define mmDMA2_CORE_ERRMSG_WDATA 0x540178 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define mmDMA2_CORE_STS0 0x540190 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay #define mmDMA2_CORE_STS1 0x540194 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204 135*e65e175bSOded Gabbay 136*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C 139*e65e175bSOded Gabbay 140*e65e175bSOded Gabbay #define mmDMA2_CORE_RD_DBGMEM_RC 0x540210 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_DESC_CNT 0x54022C 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_STS 0x540230 151*e65e175bSOded Gabbay 152*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238 155*e65e175bSOded Gabbay 156*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA2_CORE_REGS_H_ */ 157