1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_DMA0_CORE_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_DMA0_CORE_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * DMA0_CORE (Prototype: DMA_CORE) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* DMA0_CORE_CFG_0 */ 23*e65e175bSOded Gabbay #define DMA0_CORE_CFG_0_EN_SHIFT 0 24*e65e175bSOded Gabbay #define DMA0_CORE_CFG_0_EN_MASK 0x1 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay /* DMA0_CORE_CFG_1 */ 27*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_HALT_SHIFT 0 28*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_HALT_MASK 0x1 29*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 30*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 31*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 32*e65e175bSOded Gabbay #define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay /* DMA0_CORE_LBW_MAX_OUTSTAND */ 35*e65e175bSOded Gabbay #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 36*e65e175bSOded Gabbay #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay /* DMA0_CORE_SRC_BASE_LO */ 39*e65e175bSOded Gabbay #define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 40*e65e175bSOded Gabbay #define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay /* DMA0_CORE_SRC_BASE_HI */ 43*e65e175bSOded Gabbay #define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 44*e65e175bSOded Gabbay #define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF 45*e65e175bSOded Gabbay 46*e65e175bSOded Gabbay /* DMA0_CORE_DST_BASE_LO */ 47*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 48*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF 49*e65e175bSOded Gabbay 50*e65e175bSOded Gabbay /* DMA0_CORE_DST_BASE_HI */ 51*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 52*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF 53*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 54*e65e175bSOded Gabbay #define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay /* DMA0_CORE_SRC_TSIZE_1 */ 57*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 58*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay /* DMA0_CORE_SRC_STRIDE_1 */ 61*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 62*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay /* DMA0_CORE_SRC_TSIZE_2 */ 65*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 66*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay /* DMA0_CORE_SRC_STRIDE_2 */ 69*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 70*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay /* DMA0_CORE_SRC_TSIZE_3 */ 73*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 74*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay /* DMA0_CORE_SRC_STRIDE_3 */ 77*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 78*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay /* DMA0_CORE_SRC_TSIZE_4 */ 81*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 82*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay /* DMA0_CORE_SRC_STRIDE_4 */ 85*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 86*e65e175bSOded Gabbay #define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay /* DMA0_CORE_SRC_TSIZE_0 */ 89*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 90*e65e175bSOded Gabbay #define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay /* DMA0_CORE_DST_TSIZE_1 */ 93*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 94*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay /* DMA0_CORE_DST_STRIDE_1 */ 97*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 98*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay /* DMA0_CORE_DST_TSIZE_2 */ 101*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 102*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay /* DMA0_CORE_DST_STRIDE_2 */ 105*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 106*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay /* DMA0_CORE_DST_TSIZE_3 */ 109*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 110*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay /* DMA0_CORE_DST_STRIDE_3 */ 113*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 114*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay /* DMA0_CORE_DST_TSIZE_4 */ 117*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 118*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF 119*e65e175bSOded Gabbay 120*e65e175bSOded Gabbay /* DMA0_CORE_DST_STRIDE_4 */ 121*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 122*e65e175bSOded Gabbay #define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay /* DMA0_CORE_DST_TSIZE_0 */ 125*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 126*e65e175bSOded Gabbay #define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay /* DMA0_CORE_COMMIT */ 129*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 130*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 131*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 132*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 133*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 134*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 135*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_LIN_SHIFT 3 136*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_LIN_MASK 0x8 137*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 138*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 139*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 140*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 141*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 142*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 143*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 144*e65e175bSOded Gabbay #define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay /* DMA0_CORE_WR_COMP_WDATA */ 147*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 148*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay /* DMA0_CORE_WR_COMP_ADDR_LO */ 151*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 152*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay /* DMA0_CORE_WR_COMP_ADDR_HI */ 155*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 156*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay /* DMA0_CORE_WR_COMP_AWUSER_31_11 */ 159*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 160*e65e175bSOded Gabbay #define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay /* DMA0_CORE_TE_NUMROWS */ 163*e65e175bSOded Gabbay #define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 164*e65e175bSOded Gabbay #define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay /* DMA0_CORE_PROT */ 167*e65e175bSOded Gabbay #define DMA0_CORE_PROT_VAL_SHIFT 0 168*e65e175bSOded Gabbay #define DMA0_CORE_PROT_VAL_MASK 0x1 169*e65e175bSOded Gabbay #define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 170*e65e175bSOded Gabbay #define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 171*e65e175bSOded Gabbay 172*e65e175bSOded Gabbay /* DMA0_CORE_SECURE_PROPS */ 173*e65e175bSOded Gabbay #define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 174*e65e175bSOded Gabbay #define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF 175*e65e175bSOded Gabbay #define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 176*e65e175bSOded Gabbay #define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay /* DMA0_CORE_NON_SECURE_PROPS */ 179*e65e175bSOded Gabbay #define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 180*e65e175bSOded Gabbay #define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF 181*e65e175bSOded Gabbay #define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 182*e65e175bSOded Gabbay #define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 183*e65e175bSOded Gabbay 184*e65e175bSOded Gabbay /* DMA0_CORE_RD_MAX_OUTSTAND */ 185*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 186*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay /* DMA0_CORE_RD_MAX_SIZE */ 189*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 190*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF 191*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 192*e65e175bSOded Gabbay #define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 193*e65e175bSOded Gabbay 194*e65e175bSOded Gabbay /* DMA0_CORE_RD_ARCACHE */ 195*e65e175bSOded Gabbay #define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 196*e65e175bSOded Gabbay #define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF 197*e65e175bSOded Gabbay 198*e65e175bSOded Gabbay /* DMA0_CORE_RD_ARUSER_31_11 */ 199*e65e175bSOded Gabbay #define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 200*e65e175bSOded Gabbay #define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF 201*e65e175bSOded Gabbay 202*e65e175bSOded Gabbay /* DMA0_CORE_RD_INFLIGHTS */ 203*e65e175bSOded Gabbay #define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 204*e65e175bSOded Gabbay #define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF 205*e65e175bSOded Gabbay 206*e65e175bSOded Gabbay /* DMA0_CORE_WR_MAX_OUTSTAND */ 207*e65e175bSOded Gabbay #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 208*e65e175bSOded Gabbay #define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF 209*e65e175bSOded Gabbay 210*e65e175bSOded Gabbay /* DMA0_CORE_WR_MAX_AWID */ 211*e65e175bSOded Gabbay #define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 212*e65e175bSOded Gabbay #define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF 213*e65e175bSOded Gabbay 214*e65e175bSOded Gabbay /* DMA0_CORE_WR_AWCACHE */ 215*e65e175bSOded Gabbay #define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 216*e65e175bSOded Gabbay #define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF 217*e65e175bSOded Gabbay 218*e65e175bSOded Gabbay /* DMA0_CORE_WR_AWUSER_31_11 */ 219*e65e175bSOded Gabbay #define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 220*e65e175bSOded Gabbay #define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF 221*e65e175bSOded Gabbay 222*e65e175bSOded Gabbay /* DMA0_CORE_WR_INFLIGHTS */ 223*e65e175bSOded Gabbay #define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 224*e65e175bSOded Gabbay #define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF 225*e65e175bSOded Gabbay 226*e65e175bSOded Gabbay /* DMA0_CORE_RD_RATE_LIM_CFG_0 */ 227*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 228*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 229*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 230*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 231*e65e175bSOded Gabbay 232*e65e175bSOded Gabbay /* DMA0_CORE_RD_RATE_LIM_CFG_1 */ 233*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 234*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF 235*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 236*e65e175bSOded Gabbay #define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 237*e65e175bSOded Gabbay 238*e65e175bSOded Gabbay /* DMA0_CORE_WR_RATE_LIM_CFG_0 */ 239*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 240*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF 241*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 242*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 243*e65e175bSOded Gabbay 244*e65e175bSOded Gabbay /* DMA0_CORE_WR_RATE_LIM_CFG_1 */ 245*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 246*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF 247*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 248*e65e175bSOded Gabbay #define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 249*e65e175bSOded Gabbay 250*e65e175bSOded Gabbay /* DMA0_CORE_ERR_CFG */ 251*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 252*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 253*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 254*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 255*e65e175bSOded Gabbay 256*e65e175bSOded Gabbay /* DMA0_CORE_ERR_CAUSE */ 257*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 258*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 259*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 260*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 261*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 262*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 263*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 264*e65e175bSOded Gabbay #define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 265*e65e175bSOded Gabbay 266*e65e175bSOded Gabbay /* DMA0_CORE_ERRMSG_ADDR_LO */ 267*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 268*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF 269*e65e175bSOded Gabbay 270*e65e175bSOded Gabbay /* DMA0_CORE_ERRMSG_ADDR_HI */ 271*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 272*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF 273*e65e175bSOded Gabbay 274*e65e175bSOded Gabbay /* DMA0_CORE_ERRMSG_WDATA */ 275*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 276*e65e175bSOded Gabbay #define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF 277*e65e175bSOded Gabbay 278*e65e175bSOded Gabbay /* DMA0_CORE_STS0 */ 279*e65e175bSOded Gabbay #define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 280*e65e175bSOded Gabbay #define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF 281*e65e175bSOded Gabbay #define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 282*e65e175bSOded Gabbay #define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 283*e65e175bSOded Gabbay #define DMA0_CORE_STS0_BUSY_SHIFT 31 284*e65e175bSOded Gabbay #define DMA0_CORE_STS0_BUSY_MASK 0x80000000 285*e65e175bSOded Gabbay 286*e65e175bSOded Gabbay /* DMA0_CORE_STS1 */ 287*e65e175bSOded Gabbay #define DMA0_CORE_STS1_IS_HALT_SHIFT 0 288*e65e175bSOded Gabbay #define DMA0_CORE_STS1_IS_HALT_MASK 0x1 289*e65e175bSOded Gabbay 290*e65e175bSOded Gabbay /* DMA0_CORE_RD_DBGMEM_ADD */ 291*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 292*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF 293*e65e175bSOded Gabbay 294*e65e175bSOded Gabbay /* DMA0_CORE_RD_DBGMEM_DATA_WR */ 295*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 296*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF 297*e65e175bSOded Gabbay 298*e65e175bSOded Gabbay /* DMA0_CORE_RD_DBGMEM_DATA_RD */ 299*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 300*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF 301*e65e175bSOded Gabbay 302*e65e175bSOded Gabbay /* DMA0_CORE_RD_DBGMEM_CTRL */ 303*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 304*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 305*e65e175bSOded Gabbay 306*e65e175bSOded Gabbay /* DMA0_CORE_RD_DBGMEM_RC */ 307*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 308*e65e175bSOded Gabbay #define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 309*e65e175bSOded Gabbay 310*e65e175bSOded Gabbay /* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ 311*e65e175bSOded Gabbay 312*e65e175bSOded Gabbay /* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ 313*e65e175bSOded Gabbay 314*e65e175bSOded Gabbay /* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ 315*e65e175bSOded Gabbay 316*e65e175bSOded Gabbay /* DMA0_CORE_DBG_DESC_CNT */ 317*e65e175bSOded Gabbay #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 318*e65e175bSOded Gabbay #define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF 319*e65e175bSOded Gabbay 320*e65e175bSOded Gabbay /* DMA0_CORE_DBG_STS */ 321*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 322*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 323*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 324*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 325*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 326*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 327*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 328*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 329*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 330*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 331*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 332*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 333*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 334*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 335*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 336*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 337*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 338*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 339*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 340*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 341*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 342*e65e175bSOded Gabbay #define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 343*e65e175bSOded Gabbay 344*e65e175bSOded Gabbay /* DMA0_CORE_DBG_RD_DESC_ID */ 345*e65e175bSOded Gabbay 346*e65e175bSOded Gabbay /* DMA0_CORE_DBG_WR_DESC_ID */ 347*e65e175bSOded Gabbay 348*e65e175bSOded Gabbay #endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ 349